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imx8mp: DDR performance tunning

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1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Jian Li 2020-01-20 15:14:42 +08:00 committed by Peng Fan
parent dd2f41370d
commit 5865d14dde
1 changed files with 1 additions and 1 deletions
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2
board/freescale/imx8mp_evk/lpddr4_timing.c
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@ -52,7 +52,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x68070707 },
{ 0x3d40021c, 0xf08 },
{ 0x3d400250, 0x29001701 },
{ 0x3d400250, 0x00001705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
{ 0x3d400264, 0x900093e7 },