Commit graph

12 commits

Author SHA1 Message Date
Lokesh Vutla
753bae8c5d OMAP5: DPLL core lock for OMAP5432
No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2012-07-07 14:07:24 +02:00
SRICHARAN R
8de17f4617 OMAP5: palmas: Configure nominal opp vdd values
The nominal opp vdd values as recommended for
ES1.0 silicon is set for mpu, core, mm domains using palmas.

Also used the right sequence to enable the vcores as per
a previous patch from Nishant Menon, which can be dropped now.
	http://lists.denx.de/pipermail/u-boot/2012-March/119151.html

Signed-off-by: R Sricharan <r.sricharan@ti.com>
2012-05-15 08:31:23 +02:00
Nishanth Menon
3acb553439 OMAP4460: TPS Ensure SET1 is selected after voltage configuration
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
a78274b205 OMAP3+: Introduce generic logic for OMAP voltage controller
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.

With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.

NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Chris Lalancette
df65a3fe35 omap4_panda: Initialize the USB phy
During misc_init_r, make sure to setup the clocks
properly for the USB hub on the pandaboard.  With
this in place, the USB hub and the ethernet works
on the pandaboard.

Signed-off-by: Chris Lalancette <clalancette@gmail.com>
Acked-by: Aneesh V <aneesh@ti.com>
2011-12-19 17:52:44 +01:00
Sricharan
78f455c055 omap4/5: Add support for booting with CH.
Configuration header(CH) is 512 byte header attached to an OMAP
boot image that will help ROM code to initialize clocks, SDRAM
etc and copy U-Boot directly into SDRAM. CH can help us in
by-passing SPL and directly boot U-boot, hence it's an alternative
for SPL. However, we intend to support both CH and SPL for OMAP4/5.

Initialization done through CH is limited and is not equivalent
to that done by SPL. So U-Boot has to distinguish between the
two cases and handle them accordingly. This patch takes care
of doing this.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Sricharan
2e5ba48928 omap5: clocks: Add clocks support for omap5 platform.
Adding the correct configurations required for
dplls, clocks, for omap5 Soc.

Also changes are done to retain some part of the code common
for OMAP4/5 and move only the remaining to the Soc specific
directories.

Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-11-15 22:25:50 +01:00
Aneesh V
34455b04fc omap4: fix build warning due to signed unsigned comparison
Signed-off-by: Aneesh V <aneesh@ti.com>
2011-09-04 11:34:09 +02:00
Aneesh V
b4dc644291 omap4: clock init support for omap4460
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-08-03 12:49:20 +02:00
Aneesh V
d506719f7f omap4: support TPS programming
TPS62361 is the new power supply used in OMAP4460 that
supplies vdd_mpu.

VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies
vdd_iva. VCORE3 is not used in OMAP4460.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-08-03 12:49:20 +02:00
Aneesh V
2ae610f030 omap4: add sdram init support
Add support for the SDRAM controller (EMIF).

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-08-03 12:49:19 +02:00
Aneesh V
3776801d0a omap4: add clock support
Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules
3. Setting up the right voltage on voltage rails

This work draws upon previous work done for x-loader by:
	Santosh Shilimkar <santosh.shilimkar@ti.com>
	Rajendra Nayak <rnayak@ti.com>

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-08-03 12:49:19 +02:00