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omap4: support TPS programming
TPS62361 is the new power supply used in OMAP4460 that supplies vdd_mpu. VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies vdd_iva. VCORE3 is not used in OMAP4460. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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25223a68e5
commit
d506719f7f
4 changed files with 79 additions and 7 deletions
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@ -90,6 +90,10 @@ static void set_muxconf_regs_essential(void)
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do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
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sizeof(wkup_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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/* gpio_wk7 is used for controlling TPS on 4460 */
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if (omap_revision() >= OMAP4460_ES1_0)
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writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
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}
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static void set_mux_conf_regs(void)
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@ -34,6 +34,7 @@
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/utils.h>
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#include <asm/omap_gpio.h>
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#ifndef CONFIG_SPL_BUILD
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/*
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@ -421,6 +422,34 @@ static void setup_non_essential_dplls(void)
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do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK);
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}
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static void do_scale_tps62361(u32 reg, u32 volt_mv)
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{
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u32 temp, step;
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step = volt_mv - TPS62361_BASE_VOLT_MV;
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step /= 10;
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/*
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* Select SET1 in TPS62361:
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* VSEL1 is grounded on board. So the following selects
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* VSEL1 = 0 and VSEL0 = 1
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*/
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omap_set_gpio_direction(TPS62361_VSEL0_GPIO, 0);
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omap_set_gpio_dataout(TPS62361_VSEL0_GPIO, 1);
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temp = TPS62361_I2C_SLAVE_ADDR |
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(reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
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(step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
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PRM_VC_VAL_BYPASS_VALID_BIT;
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debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
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writel(temp, &prcm->prm_vc_val_bypass);
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if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
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&prcm->prm_vc_val_bypass, LDELAY)) {
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puts("Scaling voltage failed for vdd_mpu from TPS\n");
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}
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}
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static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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{
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u32 temp, offset_code;
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@ -461,7 +490,7 @@ static void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
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*/
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static void scale_vcores(void)
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{
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u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp;
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u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp, omap4_rev;
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sys_clk_khz = get_sys_clk_freq() / 1000;
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@ -481,23 +510,45 @@ static void scale_vcores(void)
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/* Disable high speed mode and all advanced features */
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writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
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omap4_rev = omap_revision();
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/* TPS - supplies vdd_mpu on 4460 */
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if (omap4_rev >= OMAP4460_ES1_0) {
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volt = 1430;
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do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
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}
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/*
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* VCORE 1 - 4430 : supplies vdd_mpu
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* VCORE 1
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*
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* 4430 : supplies vdd_mpu
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* Setting a high voltage for Nitro mode as smart reflex is not enabled.
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* We use the maximum possible value in the AVS range because the next
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* higher voltage in the discrete range (code >= 0b111010) is way too
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* high
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*
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* 4460 : supplies vdd_core
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*/
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volt = 1417;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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if (omap4_rev < OMAP4460_ES1_0) {
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volt = 1417;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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} else {
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
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}
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/* VCORE 2 - supplies vdd_iva */
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
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/* VCORE 3 - supplies vdd_core */
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
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/*
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* VCORE 3
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* 4430 : supplies vdd_core
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* 4460 : not connected
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*/
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if (omap4_rev < OMAP4460_ES1_0) {
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volt = 1200;
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do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
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}
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}
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static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
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@ -618,6 +618,7 @@ struct omap4_prcm_regs {
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#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
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#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
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/* SMPS */
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#define SMPS_I2C_SLAVE_ADDR 0x12
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#define SMPS_REG_ADDR_VCORE1 0x55
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#define SMPS_REG_ADDR_VCORE2 0x5B
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@ -626,6 +627,21 @@ struct omap4_prcm_regs {
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
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#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
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/* TPS */
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#define TPS62361_I2C_SLAVE_ADDR 0x60
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#define TPS62361_REG_ADDR_SET0 0x0
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#define TPS62361_REG_ADDR_SET1 0x1
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#define TPS62361_REG_ADDR_SET2 0x2
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#define TPS62361_REG_ADDR_SET3 0x3
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#define TPS62361_REG_ADDR_CTRL 0x4
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#define TPS62361_REG_ADDR_TEMP 0x5
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#define TPS62361_REG_ADDR_RMP_CTRL 0x6
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#define TPS62361_REG_ADDR_CHIP_ID 0x8
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#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
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#define TPS62361_BASE_VOLT_MV 500
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#define TPS62361_VSEL0_GPIO 7
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/* Defines for DPLL setup */
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#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
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#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
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@ -341,4 +341,5 @@ struct pad_conf_entry {
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#define CONTROL_SPARE_R 0x0618
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#define CONTROL_SPARE_R_C0 0x061C
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#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A
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#endif /* _MUX_OMAP4_H_ */
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