Commit graph

93 commits

Author SHA1 Message Date
Jagannadha Sutradharudu Teki
615a156167 sf: Add flag status register polling support
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.

Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
ba549de6c5 sf: Remove spi_flash_cmd_poll_bit()
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:51 +05:30
Jagannadha Sutradharudu Teki
f76b1bd08b sf: Use spi_flash_addr() in write call
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
1dcd6d0381 sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.

It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
fc207ee4db sf: Update sf read to support all sizes of flashes
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.

The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)

With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
e3ff9d51ec sf: Update sf to support all sizes of flashes
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility

The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.

As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
e612ddf593 sf: Read flash bank addr register at probe time
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.

bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.

Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:50 +05:30
Jagannadha Sutradharudu Teki
cf6b11dcda sf: Discover the bank addr commands
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.

Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-06-23 22:02:49 +05:30
Jagannadha Sutradharudu Teki
c9fcb59d7d sf: Add bank address register writing support
This patch provides support to program a flash bank address
register.

extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.

reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2013-06-23 22:02:49 +05:30
Tom Rini
348e47f766 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-06-22 07:38:12 -04:00
Jagannadha Sutradharudu Teki
60b6614ac8 cmd_sf: Add print mesgs on sf read/write commands
This patch adds a print messages while using 'sf read' and
'sf write' commands to make sure that how many bytes read/written
from/into flash device.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Tom Rini <trini@ti.com>
2013-06-03 00:04:41 +05:30
Jagannadha Sutradharudu Teki
96bbf55651 cmd_sf: Add print mesg for 'sf erase' command
This patch adds a print messages while using 'sf erase' command
to make sure that how many bytes erased in flash device.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Tom Rini <trini@ti.com>
2013-06-03 00:04:40 +05:30
Jagannadha Sutradharudu Teki
0d3b596aa3 sf: Fix sf read for memory-mapped SPI flashes
Missing return after memcpy is done for memory-mapped SPI flashes,
hence added retun 0 after memcpy done.

The return is missing in below patch
"sf: Enable FDT-based configuration and memory mapping"
(sha1: bb8215f437)

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-06-03 00:04:40 +05:30
Rajeshwari Shinde
f10b4c0e65 SF: Add driver for Gigabyte device GD25LQ and GD25Q64B
This patch adds driver for the gigabyte devices
GD25LQ and GD25Q64B required for Snow Board.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-05-20 13:47:22 +09:00
Simon Glass
bb8215f437 sf: Enable FDT-based configuration and memory mapping
Enable device tree control of SPI flash, and use this to implement
memory-mapped SPI flash, which is supported on Intel chips.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
1e566bc6db sf: Respect maximum SPI write size
Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of
bytes that can be in a write transaction. Support this by breaking the
writes into multiple transactions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
b5aec1424d sf: Add spi_flash_alloc() to create a new SPI flash struct
At present it is difficult to extend the SPI flash structure since
all devices allocate it themselves, and few of them zero all fields.
Add a new function spi_flash_alloc() which can be used by SPI devices
to perform this allocation, and thus ensure that all devices can
better cope with SPI structure changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Mike Frysinger
41e1713425 sf: unify status register writing (and thus block unlocking)
The only two drivers to write the status register do it in the same
way, so unify the implementations.  This also makes the block unlock
logic the same.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-04 23:18:17 -05:00
Mike Frysinger
c4e932ce73 sf: unify erase commands
Analysis of the flash drivers shows that they all use 0x20 if the erase
size is 4KiB, or 0xd8 if it's larger.  So with this info in hand, we can
unify all the erase functionality in one place.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-04 22:35:50 -05:00
Vadim Bendebury
1f6734cf50 sf: fix erase debug output
We want to show the length, so multiplying by sector size makes no sense.
This is a hold over from the erase code before the big refactor.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-12-05 21:55:24 +01:00
Vadim Bendebury
3f96ee3347 sf: fix debug format string warning
On some systems, we get a warning when %lu is used with size_t's, so
use the correct format string.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-21 23:05:15 +02:00
Mike Frysinger
d4aa500913 sf: unify write funcs
Once we add a new page_size field for write lengths, we can unify the
write methods for most of the spi flash drivers.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-26 16:29:27 +02:00
Mike Frysinger
2744a4e688 sf: unify write enable commands
Every spi flash uses the same write enable command, so unify this in
the common code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-07-26 16:28:21 +02:00
Patrick Sestier
bd0d19cc5f sf: kick watchdog when polling
The status polling can take a while, so make sure we kick the
watchdog after each successful poll.

Signed-off-by: Patrick Sestier <psestier@mircom.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-01 22:21:42 +02:00
Mike Frysinger
493c360721 sf: use print_size() for sector_size output
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-12 02:30:25 -04:00
Richard Retanubun
4e6a515899 sf: add struct spi_flash.sector_size parameter
This patch adds a new member to struct spi_flash (u16 sector_size)
and updates the spi flash drivers to start populating it.

This parameter can be used by spi flash commands that need to round
up units of operation to the flash's sector_size.

Having this number in one place also allows duplicated code to be
further collapsed into one common location (such as erase parameter
and the detected message).

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-12 02:15:37 -04:00
Mike Frysinger
a4c3b40b33 sf: unify read functions
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 21:00:55 +02:00
Mike Frysinger
e7b44eddbe sf: unify erase functions
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 21:00:54 +02:00
Mike Frysinger
6163045bcd sf: unify status polling for ready bit
All of the spi flash drivers implement the status register polling for
detecting the device ready state, so unify them all in a new helper
function -- spi_flash_wait_ready.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 21:00:53 +02:00
Mike Frysinger
000044d8bf sf: unify read/write helpers
These functions largely do the same exact thing, so unify them all
into one basic function.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 21:00:49 +02:00
Chong Huang
d1d9065647 sf: new driver for EON devices
Signed-off-by: Chong Huang <chuang@ucrobotics.com>
Signed-off-by: Haitao Zhang <minipanda@linuxrobot.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-12-17 08:53:55 -05:00
Reinhard Meyer
e0987e251f sf: ramtron: new spi fram driver
Supports most types that support Read-Id and the FM25H20.

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-11-10 04:26:18 -05:00
Reinhard Meyer
0d3fe2b153 sf: turn probe switch into a lookup table
This allows for arbitrarily long manufacturer ids following the JEDEC
standard of 0x7f continuation bytes.  It also makes adding new entries
easier as it's just one element in an array.  The downside is that it
increases code size a bit, but we're talking ~50 bytes.

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-12 21:08:25 -04:00
Mike Frysinger
b376bbb49f sf: move useful messages from debug to printf
At the moment, the default SPI flash subsystem is quite terse.  Errors and
successes both result in a generic message.  So move the useful errors and
useful successes to printf output by default.

While we're here, also convert the messages to use print_size().

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-06-30 23:47:08 -04:00
Thomas Chou
12c2e3bbbe spi_flash: support old STMicro parts with RES
Some old STMicro parts do not support JEDEC ID (0x9f). This patch
uses RES (0xab) to get Electronic ID and translates it to JEDEC ID.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2010-06-30 23:47:08 -04:00
Jason McMullan
d394a77950 sf: new driver for Winbond W25X16/32/64 devices
Signed-off-by: Jason McMullan <jason.mcmullan@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-11-22 23:54:18 +01:00
Mike Frysinger
4166ee58d3 sf: add GPL-2 license info
Some of the new spi flash files were missing explicit license lines.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-10-24 22:44:18 +02:00
Prafulla Wadaskar
7ce6031afc sf: new Macronix MX25xx SPI flash driver
Added macronix SF driver for MTD framework
MX25L12805D is supported and tested
TBD: sector erase implementation, other deivces support

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12 20:47:18 +02:00
Mike Frysinger
0dcdbb172c sf: always read 5 bytes for the idcode
Some SPI flash drivers like to have extended id information available
(like the spansion flash), so rather than making it re-issue the ID cmd
to get at the last 2 bytes, have the common code read 5 bytes rather than
just 3.  This also matches the Linux behavior where it always reads 5 id
bytes from all flashes.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Mingkai Hu <Mingkai.hu@freescale.com>
2009-04-02 06:50:21 -04:00
Mike Frysinger
1c5874374e sf: add driver for SST flashes
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-04-02 06:49:58 -04:00
Mike Frysinger
f773a1bbdb sf: drop DEBUG defines
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2009-04-02 06:49:49 -04:00
TsiChung Liew
7b7a869a8b mtd: SPI Flash: Support the STMicro Flash
Add MTD SPI Flash support for M25P16, M25P20, M25P32,
M25P40, M25P64, M25P80, M25P128.

Signed-off-by: Jason McMullan <mcmullan@netapp.com>
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-09-09 11:57:29 -06:00
Haavard Skinnemoen
d25ce7d24c SPI Flash subsystem
This adds a new SPI flash subsystem.

Currently, only AT45 DataFlash in non-power-of-two mode is supported,
but some preliminary support for other flash types is in place as
well.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-06-03 20:31:34 +02:00