The Colibri PXA270 has been end-of-life since quite a while and would
require more and more maintenance (e.g. DM conversions).
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
The GW74xx is based on the i.MX 8M Plus SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- PCIe Gen 3.0 switch (build option)
- USB 3.0 HUB
- USB Type-C front panel connector
- GPS
- 3-axis accelerometer
- CAN bus
- 6x GbE RJ45 front-panel jacks
- 1x IMX8M FEC RGMII GbE (with Passive PoE)
- 5x IMX8M EQOS RGMII 6 port GbE Switch
(1x with 802.3af class 5 Active PoE)
- RS232/RS485/RS422 serial transceiver
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- DigI/O header (UART/GPIO/I2C/ADC)
- 802.11ac WiFi
- Bluetooth BLE
- 3x MiniPCIe sockets with PCI/USB
- 1x M.2 Socket with USB2.0, PCIe, and dual-SIM
- PMIC
- Wide range DC input supply (8V to 60V DC)
Do the following to add support for this and future imx8mp-venice boards:
- add dts
- add DRAM config
- add PMIC config
- add IMX8MP support in spl.c and venice.c
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Gateworks produces many products from a single PCB with subloaded
components. Add an additional two levels of dtb name matching so that
for example a GW7400-A matches the dtb name of gw74xx.dtb
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Use the common GSC driver.
This allows us to do some additional cleanup:
- use the GSC driver functions
- move waiting for the EEPROM to the SPL int (it will always be ready
after this)
- move eeprom functions into eeprom file and elimate GSC_I2C_BUS
- eliminate some redundant EEPROM reads (the EEPROM must be read in
SPL before relocation, in SPL after relocation, and in U-Boot init.
All subsequent uses can use the global structure)
- remove unnecessary header files and alphabatize includes
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The TI DP83867 phy has been replaced with the MaxLinear GPY111 phy
due to part availability. Add support for it:
- increase post-reset time to 300ms per datasheet
- add tx-delay/rx-delay config
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add gpio hog support for board-specific gpio lines:
- put hogs in u-boot.dtsi so as to keep the regular dts files
in sync with the kernel. The hogs will not be put in the kernel
as that makes them un-usable by userspace as well as
re-initializes them to dt defaults overriding changes which may
have been done by bootloader commands.
- specify gpio names and initial config
- enable GPIO_HOG
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Use the common GSC driver.
This allows us to do some additional cleanup:
- rename gsc{.c,.h} to eeprom{.c.h} for clarity
- collapse eeprom_get_dev
- remove unnecessary header files and alphabatize includes
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Enable USB support for host controller and various USB ethernet
devices.
Example usage of USB Mass Storage (UMS) support:
u-boot=> mmc list
FSL_SDHC: 0
FSL_SDHC: 1
FSL_SDHC: 2 (eMMC)
u-boot=> ums 0 mmc 2
UMS: LUN 0, dev mmc 2, hwpart 0, sector 0x0, count 0xe30000
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Use PREBOOT as well. This allows a customer to just set fdt_board as
on any other module to customize the device tree for his carrier
board.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drop optional support for the ancient Apalis iMX6 V1.0 hardware which
had the UART wired as DCE rather than DTE.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This fixes the following crash when run on a Colibri iMX7S aka solo:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000:
The i.MX 7Solo has only one single USB OTG1 but no USB host port. Trying
to initialize the nonexisting port just crashes.
While at it also drop board_usb_phy_mode() which is also no longer used
in the driver model age.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
In case a customer wants to set fdtfile currently preboot overrides it
always with preboot just before the bootdelay. Use test -n to check
if fdtfile is already set and only set it if nothing got touched manually
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
For recovery purpose allow booting via SDP over USB as well.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add missing support of FIT-images and enable a verbosity for
this feature.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drop legacy nfsboot script in favor of distroboot DHCP boot.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Use the same name of DHCP Distroboot script as in regular eMMC case.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
As video support is very specific depending on the exact display
customisation we decided to disable video support for all out modules
by default.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Drop Apalis iMX8X platform as it never left sample state and is no
longer supported.
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Add DT bindings for a subset of GPCv2 which handles USB and PCIe PDs,
HSIOMIX PD controller and missing USB PD properties. This is required
to bring up the DWC3 USB controller up.
This is based on linux next and patches which are still pending
review, but which are likely going to be part of Linux 5.19:
b2d67d7bdf74 ("arm64: dts: imx8mp: disable usb3_phy1")
290918c72a29 ("arm64: dts: imx8mp: Add memory for USB3 glue layer to usb3 nodes")
https://www.spinics.net/lists/arm-kernel/msg958501.html
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX8MP glue needs to be configured based on a couple of DT
properties, implement .glue_configure callback to parse those DT
properties and configure the glue accordingly.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Angus Ainslie <angus@akkea.ca>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Rename the select_dr_mode callback to glue_configure, the callback is
used for more than enforcing controller mode even on the TI chips, so
change the name to a more generic one. No functional change.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Angus Ainslie <angus@akkea.ca>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add trivial driver for i.MX8MP HSIOMIX handling. This is responsible
for enabling the GPCv2 power domains and clock for USB 3.0 and PCIe
in the correct order. Currently supported is the USB 3.0 part which
can be tested, PCIe support should be easy to add.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add i.MX8MP power domain handling into the driver. This is based on the
Linux GPCv2 driver state which is soon to be in Linux next.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Implement power_domain_get_by_name() convenience function which parses
DT property 'power-domain-names' and looks up power domain by matching
name.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Simon Glass <sjg@chromium.org>
This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework
the driver based on Linux GPCv2 driver to directly control the GPCv2
block instead of using SMCCC calls. This way, U-Boot can operate the
i.MX8M power domains without depending on anything else.
This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power
domains are not supported to save space, since they are not useful in
the bootloader. The only domains kept are ones for HSIO, PCIe, USB.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The arch/arm/include/asm/arch-imx8m/power-domain.h is not included
anywhere except in drivers/power/domain/imx8m-power-domain.c, just
inline the content and drop the header. No functional change.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
In case the power domain node structure is gpc@303a0000/pgc/power-domain@N,
do not bind power domain driver to the 'pgc' node, but rather descend into
it and only bind power domain drivers to power-domain@N subnodes. This way
we do not waste one useless driver instance associated with 'pgc' node.
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
In case the ops is not implemented, return 0 in the core right away.
This is better than having multiple copies of functions which just
return 0 in each power domain driver. Drop all those empty functions.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Simon Glass <sjg@chromium.org>
The div loop uses reassign and reuse parent_rate, which causes
the parent rate reference to be wrong after the first loop, the
resulting clock becomes incorrect for div != 1.
Fixes: 829e06bf41 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock")
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
DT node name should be generic, therefore rename atsha204a@64 to crypto@64.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Turris Omnia uses first MAC address from OTP for second ethernet interface.
Second MAC address for third interface and third MAC address for first
interface.
Other Turris routers do not have this rotate by one mapping. So add
function parameter for specifying id of the first ethernet interface.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Atsha device is used prior relocation and at this early stage BSS does not
have to be ready yet. So do not cache Atsha device in BSS.
Fixes support for other Turris routers.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
OTP code is not Atsha generic but also it is not Omnia specific. It is
common for all Turris routers which use Atsha cryptochip for storing OTP.
So move this common Turris specific Atsha OTP code from Turris Omnia into
separate file. It will be used also by other Turris routers.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Implement write support for Security OTP values via mailbox API commands
MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE.
Write support for North and South Bridge OTPs are not implemented as these
OTPs are already burned in factory with some data.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
U-Boot SPL is on 32-bit mvebu executed by the BootROM. And BootROM expects
that U-Boot SPL returns execution back to the BootROM. Vectors during
execution of U-Boot SPL should not be changed as BootROM does not expect it
and uses its own vectors. So do not overwrite vectors in SPL build.
Signed-off-by: Pali Rohár <pali@kernel.org>
fstat()'s st_size works only for regular files. lseek() with SEEK_END works
also for block or MTD devices. This replacement allows kwboot to load
kwbimage from /dev/mtd0 for booting another device over /dev/ttyS0.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse
is used for secure boot and each line is 64 bits long + 1 lock bit. LD
eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for
Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot
already contains HD eFuse reading and programming support.
This patch implements LD eFuse reading support. LD 0 line is mapped to
U-Boot fuse bank 64 and LD 1 line to fuse bank 65.
LD 0 Marvell Internal Use line seems that was burned in factory with some
data and can be read by U-Boot fuse command:
=> fuse read 64 0 9
LD 1 General Purpose Data line is by default empty and can be read by
U-Boot fuse command:
=> fuse read 65 0 9
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Update the current uDPU defconfig with following changes:
* Disable CONFIG_SPI_BOOT, its not needed for booting and the device boots
from eMMC anyway.
* Disable CONFIG_SYS_CONSOLE_INFO_QUIET, there is no need to diverge from
other boards by not priting the console device
* Enable CONFIG_CMD_MTD in order to allow use of the MTD tool
* Disable CONFIG_CMD_MTDPARTS, with MTD now being able to parse partitions
from DTS there is no need for it, the default MTDPARTS were incorrect
anyway
* Enable CONFIG_MMC_HS200_SUPPORT, the eMMC used support both HS200 and
HS400 modes, so enable at least HS200 because Xenon driver does not
support HS400 currently
* Replace CONFIG_SPI_FLASH_BAR with CONFIG_SPI_FLASH_SFDP_SUPPORT
Utilize SFDP parsing instead of relying on the extended address registers
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
uDPU is a bit of a specific device in that it does not have any copper
ports nor any ethernet PHY-s but 2 SFP ports.
This is an issue since MVNETA requires a PHY phandle or a fixed-link to
be defined under its node.
Since U-boot has no SFP support this is reasonable in order to know how
to configure the MAC.
However this also means that networking does not work on uDPU at all
currently, and fails with:
uDPU>> dhcp
Could not get PHY for neta@30000: addr 0
phy_connect failed
Could not get PHY for neta@40000: addr 1
phy_connect failed
So, to provide working networking using only SFP-s let add the fixed-link
at 1G which is much more common than 2.5G SFP-s as well as disable the
TX_DISABLE pins like done on Armada 7040 and 8040 platforms.
Since uDPU is not using any of the GPIO-s on the SB controller for any
purpose other than GPIO, a call to the pinctrl must be made in order for
it to get probed and thus register the SB GPIO bank, otherwise SB GPIO-s
are not registered at all.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Add support for handling SFP TX disable for MVNETA in the same fashion as
to what MVPP2 is doing in order to enable using SFP-s.
This allows using ethernet on SFP only boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
It is not possible for the A53 core (on which U-Boot is running) to read it
directly. For this purpose Marvell defined mbox API for sending OTP
commands between CM3 and A53 cores.
Implement these Marvell fuse reading mbox commands via U-Boot fuse API.
Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44
banks and words 0-2).
Note that of the 67 bits, the 3 upper bits are: 1 lock bit and 2
auxiliary bits (meant for testing during the manufacture of the SOC, as
I understand it).
Also note that the lock bit and the auxiliary bits are not readable
via Marvell commands.
With CZ.NIC's commands the lock bit is readable.
Write support is not implemented yet.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Allow to specify input parameters, define all available mbox commands
supported by CZ.NIC's secure firmware and also Marvell's fuse.bin firmware
and fix parsing response from Marvell OTP commands.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
