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imx: power-domain: Add i.MX8MP support

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Add i.MX8MP power domain handling into the driver. This is based on the
Linux GPCv2 driver state which is soon to be in Linux next.

Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut 2022-04-13 00:42:53 +02:00 committed by Stefano Babic
parent 63c390a1ea
commit 2e760f180d
2 changed files with 125 additions and 0 deletions
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79
drivers/power/domain/imx8m-power-domain.c
View file

@ -20,11 +20,13 @@
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/power/imx8mn-power.h>
#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/power/imx8mq-power.h>
DECLARE_GLOBAL_DATA_PTR;
#define GPC_PGC_CPU_MAPPING 0x0ec
#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
#define IMX8M_PCIE2_A53_DOMAIN BIT(15)
#define IMX8M_OTG2_A53_DOMAIN BIT(5)
@ -38,6 +40,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@ -53,8 +63,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
#define GPC_M4_PU_PDN_FLG 0x1bc
#define IMX8MP_GPC_PU_PWRHSK 0x190
#define GPC_PU_PWRHSK 0x1fc
#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
@ -63,6 +79,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23)
#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@ -80,6 +99,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX8MN_PGC_OTG1 18
#define IMX8MP_PGC_PCIE 13
#define IMX8MP_PGC_USB1 14
#define IMX8MP_PGC_USB2 15
#define IMX8MP_PGC_HSIOMIX 29
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@ -244,6 +268,58 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
};
#endif
#ifdef CONFIG_IMX8MP
static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
[IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
.bits = {
.pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
.map = IMX8MP_PCIE_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_PCIE),
},
[IMX8MP_POWER_DOMAIN_USB1_PHY] = {
.bits = {
.pxx = IMX8MP_USB1_PHY_Pxx_REQ,
.map = IMX8MP_USB1_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_USB1),
},
[IMX8MP_POWER_DOMAIN_USB2_PHY] = {
.bits = {
.pxx = IMX8MP_USB2_PHY_Pxx_REQ,
.map = IMX8MP_USB2_PHY_A53_DOMAIN,
},
.pgc = BIT(IMX8MP_PGC_USB2),
},
[IMX8MP_POWER_DOMAIN_HSIOMIX] = {
.bits = {
.pxx = IMX8MP_HSIOMIX_Pxx_REQ,
.map = IMX8MP_HSIOMIX_A53_DOMAIN,
.hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
.hskack = IMX8MP_HSIOMIX_PWRDNACKN,
},
.pgc = BIT(IMX8MP_PGC_HSIOMIX),
.keep_clocks = true,
},
};
static const struct imx_pgc_regs imx8mp_pgc_regs = {
.map = IMX8MP_GPC_PGC_CPU_MAPPING,
.pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
.pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
.hsk = IMX8MP_GPC_PU_PWRHSK,
};
static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
.domains = imx8mp_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
.pgc_regs = &imx8mp_pgc_regs,
};
#endif
static int imx8m_power_domain_on(struct power_domain *power_domain)
{
struct udevice *dev = power_domain->dev;
@ -457,6 +533,9 @@ static const struct udevice_id imx8m_power_domain_ids[] = {
#endif
#ifdef CONFIG_IMX8MN
{ .compatible = "fsl,imx8mn-gpc", .data = (long)&imx8mn_pgc_domain_data },
#endif
#ifdef CONFIG_IMX8MP
{ .compatible = "fsl,imx8mp-gpc", .data = (long)&imx8mp_pgc_domain_data },
#endif
{ }
};

46
include/dt-bindings/power/imx8mp-power.h Normal file
View file

@ -0,0 +1,46 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
*/
#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0
#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1
#define IMX8MP_POWER_DOMAIN_USB1_PHY 2
#define IMX8MP_POWER_DOMAIN_USB2_PHY 3
#define IMX8MP_POWER_DOMAIN_MLMIX 4
#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5
#define IMX8MP_POWER_DOMAIN_GPU2D 6
#define IMX8MP_POWER_DOMAIN_GPUMIX 7
#define IMX8MP_POWER_DOMAIN_VPUMIX 8
#define IMX8MP_POWER_DOMAIN_GPU3D 9
#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10
#define IMX8MP_POWER_DOMAIN_VPU_G1 11
#define IMX8MP_POWER_DOMAIN_VPU_G2 12
#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13
#define IMX8MP_POWER_DOMAIN_HDMIMIX 14
#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15
#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16
#define IMX8MP_POWER_DOMAIN_HSIOMIX 17
#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18
#define IMX8MP_HSIOBLK_PD_USB 0
#define IMX8MP_HSIOBLK_PD_USB_PHY1 1
#define IMX8MP_HSIOBLK_PD_USB_PHY2 2
#define IMX8MP_HSIOBLK_PD_PCIE 3
#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
#define IMX8MP_MEDIABLK_PD_ISI 3
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
#define IMX8MP_MEDIABLK_PD_ISP2 6
#define IMX8MP_MEDIABLK_PD_ISP1 7
#define IMX8MP_MEDIABLK_PD_DWE 8
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9
#endif