* convert all files cpu/../at91 to use at91_gpio driver syntax
* change AT91_PINP([A-F])(\d+) to AT91_PIO_PORT\1, \2
this makes all 160 AT91_PINPxxx defines obsolete
* AT91_PINPxxx defines and gpio.h can be remove, if all boards converted to new SoC access
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
In function get_osc_clk_speed(), do not change/ update
the divider for SYS_CLK as it can has cascading effect
on the other derived clocks.
Sudden change in divider value can lead to inconsistent
behavior in the system - often leading to crashes.
The problem was found when working with OMAP3EVM using
DM3730 processor card.
The patch has been tested with OMAP3530 on OMAP3EVM as
well
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Hiremath Vaibhav <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Commit cbb0cab1d9 broke some platforms which used kgdb code but
didn't actually include kgdb.h. So include kgdb.h in all the relevant
traps code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Recently this compilation error occurs:
Configuring for ML2 board...
traps.c: In function 'MachineCheckException':
traps.c:159: error: 'debugger_exception_handler' undeclared (first use
in this function)
traps.c:159: error: (Each undeclared identifier is reported only once
traps.c:159: error: for each function it appears in.)
This patch now fixes it by including kgdb.h
Signed-off-by: Stefan Roese <sr@denx.de>
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
* enable driver with CONFIG_DRIVER_AT91EMAC
* generic PHY initialization
* modify AT91RM9200 boards to use NET_MULTI driver
* the drivers has been tested with LXT971 Phy and DM9161 Phy at
MII and RMII interface
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Add CONFIG_PRELOADER/CONFIG_NAND_SPL support for nand booting
to arm926ejs/start.S
This is derived from CONFIG_PRELOADER support in arm1136/start.S
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Scott Wood <scottwood@freescale.com>
Add a disable sub-command to the cpu command that allows for disabling
cores in multicore processors. This can be useful for systems that are
using multicore chips but aren't utilizing all the cores as a way to
reduce power and possibly improve performance.
Also updated an added missing copyright.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
r14 is not supposed to be clobbered by functions. Switch
to r12 and call GET_GOT when needed. This will allow u-boot
to loose the -ffixed-r14 gcc option.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Using the GOT in IRQ handlers requires r14 to be -ffixed-r14.
Avoid this by relocatate transfer_to_handler too.
This will allow to free up r14 later on.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Since 1.0 and 2.0 use different snum table,
we fixup the snum value according to SPRN_SVR.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The real clock divider is 4 times of the bits LCRR[CLKDIV],
according the latest RevF RM.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This reverts commit bc20f9a952.
The original code was correct. I clearly need glasses or a brown
paper bag.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits
instead of 4.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Content of the RSR is put into gd early so we can output it together
with the CPU info. The clearing of gd in board_init_f is redundant for
this architecture as it is done in cpu_init_f so we remove it.
Signed-off-by: Detlev Zundel <dzu@denx.de>
SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers
Signed-off-by: Vipin <vipin.kumar@st.com>
As per coding guidlines, it is good to maintain proper ordering
in the makefiles.
This was missed during initial coding, corrected here.
This was discovered during orion5x code review
Thanks to Albert Aribaud for this.
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.
l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This is not only a cosmetic change as it fixes the real bug of board
reset not working with the ELDK 4.2 toolchain.
Signed-off-by: Detlev Zundel <dzu@denx.de>
On platforms where SPD EEPROM and another EEPROM have adjacent
I2C addresses SPD_EEPROM_ADDRESS should be defined as a single
element array, otherwise DDR2 setup code would fail with the
following error:
ERROR: Unknown DIMM detected in slot 1
However, fixing SPD_EEPROM_ADDRESS would result in another
error:
ERROR: DIMM's DDR1 and DDR2 type can not be mixed.
This happens because initdram() routine does not explicitly
initialize dimm_populated array. This patch fixes the problem.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Bootstrap options G and F are reported incorrectly (G instead
of F and vice versa). This patch fixes this.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
When referring to PCIe and USB 'endpoint' is the standard naming
convention.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
Need to reload the loop counters to keep from corrupting hardware loops.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Crashes rarely happen in the CPLB miss handler compared to the rest of
U-Boot code, so disable hardware tracing when processing misses. This
way a crash due to other functions will be shown properly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The single initcode function was growing unwieldy, so split it up the
distinct steps into their own function. This should making digesting the
result much easier on people.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The length of the sections is fixed at link time, so let the linker do the
calculation rather than doing it ourselves at runtime.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:
Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.
The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
