Commit graph

69001 commits

Author SHA1 Message Date
Patrick Delaunay
67f9f11f19 stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Alexandru Gagniuc
c981d67a04 mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilities
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of
struct mmc_config from devicetree.
The same logic is duplicated in stm32_sdmmc2_probe(). Use
mmc_of_parse(), which is more generic.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-21 18:11:56 +02:00
Alexandru Gagniuc
f80b8ac69b mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no
additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed"
is used for MMC HS at both 26MHz and 52MHz.

Use the same approach and enable MMC_CAP(MMC_HS_52) host capability
when "cap-mmc-highspeed" is found in the devicetree. In the event an
MMC card doesn't support 52 MHz, it will be clocked at a speed based
on its EXT CSD, even on 52 MHz host controllers

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 09:57:14 +02:00
Ralph Siemsen
b0b08ce0b7 arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a8 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-21 11:45:54 +08:00
Tom Rini
adc0c39633 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- Assorted R-Car Gen3 updates
2020-10-20 08:02:53 -04:00
Tom Rini
f216259927 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- MediaTek USB host support
2020-10-20 08:01:46 -04:00
Lad Prabhakar
b2d7a163ab pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.9
Sync the R8A77990 SoC PFC tables with Linux 5.9 , commit bbf5c979011a.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Lad Prabhakar
a3c1fd6393 clk: renesas: Import R8A774C0 clock tables from Linux 5.9
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
e9d91b82fe clk: renesas: Add R8A774E1 clock tables
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:52 +02:00
Biju Das
54db9e8b8f clk: renesas: Add R8A774B1 clock tables
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
fc5e552209 arm: dts: r8a774c0: Import DTS from Linux 5.9
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Lad Prabhakar
051f1499c9 arm: renesas: Add config option for R8A774C0 SoC
Add config support for RZ/G2E (a.k.a R8A774C0) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:51 +02:00
Biju Das
aca749a90f arm: renesas: Add config option for R8A774E1 SoC
Add config support for RZ/G2H(a.k.a R8A774E1) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
4e4c0e5e42 arm: renesas: Add config option for R8A774B1 SoC
Add config support for RZ/G2N(a.k.a R8A774B1) SoC.

Also fixed the alignment issue on R8A774A1 config.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
f4c5f97925 clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock
Add RPC entry into the R8A774A1 clock driver tables.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Biju Das
2f220c639a spi: renesas_rpc_spi: Add R-Car Gen3 and RZ/G2 fallback compatibility string
Add fallback compatibility string for R-Car Gen3 and RZ/G2.

Also sorted the compatible string as per SoC ID.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20 12:56:46 +02:00
Chunfeng Yun
0cd791ced9 MAINTAINERS: add USB driver to ARM MEDIATEK
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK,
and add myself as a maintainer for it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
d2eb5a3fb8 configs: mt8512: enable fastboot and USB host related configs
Enable mtu3, xhci, tphy drivers.
Device mode: enable fastboot;
Host mode: enable USB, FAT commands, and fixed regulator,
mass storage drivers;
Due to device mode is enabled by default, comment out
the host mode config here.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
d6fa8db8b9 arm: dts: mt8512: add usb related nodes
Add usb, usb phy, and fixed regulators nodes

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
252bd2e3ca usb: gadget: Add bcdDevice for the MTU3 USB Gadget Controller
Add an entry in usb_gadget_controller_number() for the MTU3
gadget controller. It is used to bind the USB Ethernet driver.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
e09b88cd08 usb: add MediaTek USB3 DRD driver
This patch adds support for the MediaTek USB3 DRD controller,
its host side is based on xHCI, this driver supports device mode
and host mode.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
d92e866f60 usb: common: add define of usb_speed_string()
There is only declaration of usb_speed_string(), but no definition,
so add it to avoid build error when call it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
a4de6e380f usb: add USB_SPEED_SUPER_PLUS
Add enum USB_SPEED_SUPER_PLUS for USB3.1

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
78fe97b96e dt-bindings: usb: mtu3: add bindings for MediaTek USB3 DRD
Add dt-binding for MediaTek USB3 DRD Driver which it's ported
from the Linux kernel DTS binding:
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
Commit ID:
34d0545978b6 ("dt-bindings: usb: mtu3: fix typo of DMA clock name")

Due to Dual-Role switch is not supported in Uboot, some properties
are removed or changed.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Chunfeng Yun
8faef3c756 dt-binding: usb: add bindings for some common properties
Add bindings for common properties, include maximum-speed,
dr_mode and phy_type

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Naoki Hayama
a93cff24b1 usb: musb-new: Fix typo in caution message
%s/Occured/Occurred/

Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
2020-10-20 00:48:58 +02:00
Chance.Yang
3065680235 usb: dwc2: Fix control OUT transfer issue
In buffer DMA mode, gadget should re-configure EP 0 to received SETUP
packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes)
and EP 0 is in WAIT_FOR_SETUP state.

Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT
received from RxFifo and wriiten to the external memory.

Signed-off-by: Chance.Yang <chance.yang@vatics.com>
2020-10-20 00:48:58 +02:00
Heinrich Schuchardt
3fade88686 usb: xhci: avoid type conversion of void *
void * can be assigned to any pointer variable. Avoid unnecessary
conversions.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-20 00:48:58 +02:00
Patrick Wildt
42f804fbba efi_loader: fix use after free in receive path
With DM enabled the ethernet code will receive a packet, call
the push method that's set by the EFI network implementation
and then free the packet.  Unfortunately the push methods only
sets a flag that the packet needs to be handled, but the code
that provides the packet to an EFI application runs after the
packet has already been freed.

To rectify this issue, adjust the push method to accept the packet
and store it in a temporary buffer.  The EFI application then gets
the data copied from that buffer.  This way the packet is cached
until is is needed.

The DM Ethernet stack tries to receive 32 packets at once, thus
we better allocate as many buffers as the stack.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19 22:59:53 +02:00
Patrick Wildt
36ea0cab26 net: add a define for the number of packets received as batch
With a define for the magic number of packets received as batch
we can make sure that the EFI network stack caches the same amount
of packets.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-19 22:59:53 +02:00
Tom Rini
7ec87e4192 Second set of u-boot-atmel features for 2021.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAl+NMmQcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyLnEB/0cWFfjDfCMY1o7R4QX
 DeDRlD6k6acQWlwa5EiRKwpbPMJKrSI/m5alMCYZG6YHvGtzihqnqohz3gl1sepi
 W7eyyyFsM4hqe4P3lSETJRGWe/O8bNkoa0hBzqZ9btqw2OJLBu4JYB+zKgz8kaDY
 jzkGLgaaK6wtG3rEu+q4fjzp1y9kuz31WnN+9qS8jd/9UH13XKCkJl9TfY5pLfgc
 mmbn2NWtAhi91uShcnIsOpLaNm23IV0ITa22etB9F1docZuUrbhOtiIF45AADjpG
 /xtkV3dEVGml3N/17RizgOwxX3xughG0ak9xifsK6tfgqfVhaGMgkToNNBM+1ddm
 rZZM
 =hF12
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2021.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features for 2021.01 cycle:

This feature set brings the rework of the clock tree for sam9x60 SoC.
This makes the clock tree fully compatible with Common Clock Framework
and allows full clock configuration in U-Boot. This means that the
sam9x60 boards can boot now using U-Boot.
This also includes the definitions for sam9x60 SiPs and a divisor fix
for the clock on sama7g5 SoC.
2020-10-19 09:29:05 -04:00
Eugen Hristev
dc470834a1 clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock.
Adapt the characteristics accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Eugen Hristev
dff3904254 clk: at91: clk-master: add 5th divisor for mck master
clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Nicolas Ferre
db228c5b46 ARM: at91: Add chip ID for SAM9X60 SiP
SAM9X60 SiP (System in Package) are added for SoC identification.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
42f2dfa789 ARM: dts: sam9x60: use alphabetical order
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
6973701e27 configs: sam9x60ek: update defconfigs for CCF
Update defconfigs for using common clock framework compatible
clocks.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
c37d59a170 ARM: dts: sam9x60: use CCF compatibles for PMC
Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
dbe10b6274 ARM: dts: sam9x60: use slow clock CCF compatible bindings
Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
5dff16db16 ARM: dts: sam9x60: use u-boot,dm-pre-reloc
Use u-boot,dm-pre-reloc for slow xtal and main xtal.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
ffd204f347 ARM: dts: sam9x60ek: add clock frequencies to board file
Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
a64862284f clk: at91: sam9x60: add support compatible with CCF
Add SAM9X60 clock support compatible with CCF.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Claudiu Beznea
53040bc4d9 board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDR
Heap base address is computed based on SYS_INIT_SP_ADDR by
subtracting the SYS_MALLOC_F_LEN value in
board_init_f_init_reserve().

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19 09:19:53 +03:00
Tom Rini
e3e9bfab46 - add dw-mipi-dsi phy timings and Tx escape clock configuration
- fix pwm backlight duty cycle calculation
  - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
 -----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCX4ylng4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXA1/AJ9dbNeaZIbKIrocGOHWo8nLWdOaJwCeKwLgtlUm
 R4plRt7YvpS0DByO5V0=
 =drHB
 -----END PGP SIGNATURE-----

Merge tag 'video-for-2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

 - add dw-mipi-dsi phy timings and Tx escape clock configuration
 - fix pwm backlight duty cycle calculation
 - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
2020-10-18 21:19:06 -04:00
Patrick Delaunay
8fc78fc73b configs: migrate CONFIG_BMP_16/24/32BPP to defconfigs
Done with:
./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:27:01 +02:00
Patrick Delaunay
f9a48654ee configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigs
Done with:
./tools/moveconfig.py VIDEO_BMP_RLE8

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:26:14 +02:00
Patrick Delaunay
0ed6c0f9cb configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigs
Done with:
./tools/moveconfig.py VIDEO_BMP_GZIP

The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN
are not activated in these defconfigs:
- trats_defconfig
- s5pc210_universal_defconfig
- trats2_defconfig

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:25:28 +02:00
Dario Binacchi
76c2ff3e5f video: backlight: fix pwm's duty cycle calculation
For levels equal to the maximum value, the duty cycle must be equal to
the period.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18 15:07:33 +02:00
Dario Binacchi
f9b94055bd video: backlight: fix pwm data structure description
The description of the 'max_level' field was incorrectly assigned to the
'min_level' field.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-18 15:06:56 +02:00
Neil Armstrong
01c9857fa8 video: dw-mipi-dsi: permit configuring the escape clock rate
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency
higher than 10MHz for the TX Escape Clock, thus make the target rate
configurable.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18 10:36:05 +02:00
Neil Armstrong
b53c122631 video: dw-mipi-dsi: driver-specific configuration of phy timings
The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.

To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.

This is based on the Linux commit [1] and adapted to the U-Boot driver.

[1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18 10:35:06 +02:00