Commit graph

164 commits

Author SHA1 Message Date
Tom Rini
f10d86d3ff Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-08 13:50:38 -05:00
Marek Vasut
653cda8f66 dt: socfpga: Replace num-chipselect with num-cs
This optional DT property is called 'num-cs', so repair the misnomers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-07 12:13:30 +05:30
Marek Vasut
7411486253 dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi
Linux now also contains SPI driver, yet the name is 'snps,dw-apb-ssi'.
Fix the naming before we have to support both names.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2015-01-06 16:02:58 +05:30
Sjoerd Simons
9332274989 cros-ec-keyboard: Synchronize DT binding from linux
The ChromeOS EC keyboard is used by various different chromebooks. Peach
pi being the third board in the u-boot tree to use it (snow and peach
pit the other two). Rather then embedding the same big DT node in the
peach-pi DT again, copy the dtsi snippit & bindings documentation from
linux and include it in all 3 boards.

This slightly changes the dt bindings in u-boot:
  * google,key-rows becomes keypad,num-rows
  * google,key-colums becomes keypad,num-colums
  * google,repeat-delay-ms and google,repeat-rate-ms are no longer used
    and replaced by hardcoded values (similar to tegra kbc)

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2015-01-05 17:45:16 -07:00
Tom Rini
a74a4a86a5 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-01-01 15:10:39 -05:00
Sjoerd Simons
ce88a25cc2 odroid-XU3: Add entry for DTS EHCI GPIO
Add samsung,vbus-gpio information for the XU3. This allows the usage of
the EHCI controller on the XU3, which is connected to the SMSC LAN9514
chip (usb hub + network).

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:48:01 +09:00
Sjoerd Simons
307e90e617 Exynos5800: The Peach-Pi board does not have a Parade video bridge
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the
Pi. So drop it from  device-tree

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:38:22 +09:00
Hyungwon Hwang
6207604f9c Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:37:10 +09:00
Thierry Reding
6e2fca94ff ARM: tegra: Enable PCIe on Jetson TK1
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
9c46e6cb45 ARM: tegra: Add Tegra124 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra124 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
12e5f6acda ARM: tegra: Add GIC for Tegra124
Add a device tree node for the GIC v2 found on the Cortex-A15 CPU
complex of Tegra124. U-Boot doesn't use this but subsequent patches will
add device tree nodes that reference it by phandle.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
affe026928 ARM: tegra: Enable PCIe on Beaver
The Beaver has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network device driver so that the device can
boot over the network.

In addition the board has a mini-PCIe expansion slot.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
5a2c96a0e5 ARM: tegra: Enable PCIe on Cardhu
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
a1811bc5b9 ARM: tegra: Add Tegra30 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
cd99876120 ARM: tegra: Add GIC for Tegra30
Add a device tree node for the GIC found on Tegra30. U-Boot doesn't use
it directly but subsequent patches will add device tree nodes that
reference it by phandle.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
7dd8738f08 ARM: tegra: Enable PCIe on TrimSlice
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
65d2465d5d ARM: tegra: Add Tegra20 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
b02f3e0c2d ARM: tegra: Enable XUSB pad controller on Jetson TK1
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
78e9f1c4f3 ARM: tegra: Add XUSB pad controller on Tegra124
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Marcel Ziswiler
839e4f7c66 ARM: tegra: colibri_t30: comment style fix
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 12:47:11 -07:00
Masahiro Yamada
490f55c4a6 ARM: UniPhier: fix property names of aliases nodes of device trees
The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:01 +09:00
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Allen Martin
a6c7b46181 ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.

The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
2014-12-11 13:18:44 -07:00
Simon Glass
754204b5c2 tegra: dts: Sync tegra124.dtsi with linux kernel
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-12-11 13:18:44 -07:00
Simon Glass
6ee350bb93 dts: Bring in Chrome OS keyboard device tree definition
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Masahiro Yamada
230ce30a51 ARM: UniPhier: add device tree sources for PH1-sLD3
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09 00:08:26 +09:00
Masahiro Yamada
f5fd7afcd5 ARM: UniPhier: add more device nodes to device tree
Add I2C controller and NAND controller devices.  Fix indentation too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09 00:05:46 +09:00
Stefan Roese
369164042e arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct for the Designware SPI
controllers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
ae79e2d298 arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
2014-12-06 13:52:47 +01:00
Stefan Roese
60896653d5 arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver
Without this alias, DM based probing does not work. So lets add this
alias to get the bus numbering correct.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
881f6a448f arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi
This DT node is taken from the Rocketboard.org Linux repsitory. And
is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-06 13:52:46 +01:00
Stefan Roese
5bf1f1ed13 arm: socfpga: dts: Move to SPDX license identifiers
The socfpga dts files are copied from the Rocketboards.org repository.
In U-Boot we usually replace the full-blown license header text with
the SPDX license identifiers. Lets do this for these new dts files
as well.

I just forgot to do this while adding the DT support for socfpga.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
2014-12-06 13:51:54 +01:00
Masahiro Yamada
149c751dc7 usb: UniPhier: support OF configuration
If CONFIG_OF_CONTROL is defined, search device tree nodes that are
compatible with "panasonic,uniphier-ehci" and take the base address
from their "reg" property.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
625177d27e serial: UniPhier: support OF configuration
This commit implements the ofdata_to_platdata handler for the UniPhier
serial driver and adds serial device nodes to the device tree sources.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:21:01 +09:00
Masahiro Yamada
509eb67802 ARM: UniPhier: add device tree sources
This commit adds basic device tree sources for UniPhier SoCs/boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-28 02:20:56 +09:00
Suriyan Ramasami
6a23c6533c arm: odroid: usb: add support for usb host including ethernet
This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.

Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:33:22 +09:00
Sjoerd Simons
c2056157f8 exynos: dts: Correct USB vbus-gpio numbering for Snow
The current vbus GPIOs on snow make very little sense, their number is
far above the maximum. As a result, USB doesn't work on snow.

Correct the GPIO numbering so they match the current scheme for exynos5.
Tested both EHCI and XHCI to correctly work after this change.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:12:30 +09:00
Akshay Saraswat
e6b723fc70 Exynos5800: Add DTS for new board Peach-Pi
We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi
differs from Peach-Pit in configuration factors like display
resolution, memory size, SoC version etc.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-11-17 19:03:38 +09:00
Tom Rini
3deb013ae7 Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze 2014-11-13 08:38:17 -05:00
Tom Rini
c88eaea0a0 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-11-11 16:59:44 -05:00
Peter Crosthwaite
9757b65bef arm: dts: zynq: Add digilent ZYBO board dts
It's a Zynq board similar in design to the currently supported ones.
512MB of RAM and UART1 is used.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-11-11 11:02:07 +01:00
Stefan Roese
51c580c6c9 arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target
This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
"socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
support.

Until this patch, the only SoCFPGA U-Boot target in mainline is
"socfpga_cyclone5". This build target is not (yet) changed to support
DT. So nothing changes for this target. Even though the long-term
goal should be to move all SoCFPGA targets over to DT.

One of the reasons to enable DT support in SoCFPGA is, that I need to
support multiple different SPI controllers for this platform. This is
the QSPI Cadence controller and the Designware SPI master controller.
Both are implemented in the SoCFPGA. And enabling both controllers is
only possible by using the new driver model (DM). The DM SPI code
only supports DT based probing. So it was easier to move SoCFPGA to
DT than to add the (deprecated) platform-data based probing to the
DM SPI suport.

Note that the image with the dtb embedded is u-boot-dtb.img. This needs
to be used now for those DT enabled boards instead of u-boot.img.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Vince Bridgers <vbridger@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2014-11-07 15:58:31 +01:00
Simon Glass
1a81cf8399 dm: sunxi: Add support for serial using driver model
Add a driver for the designware serial UART used on sunxi. This just
redirects to the normal ns16550 driver.

Add a stdout-path to the device tree so that the correct UART is chosen.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Simon Glass
57f878efe5 dm: sunxi: Add a new config for an FDT-based pcDuino3
For now we won't want to mess with the existing configurations. Create a
new one which will enable device tree and driver model. Note that this
brings the device tree binary into u-boot-sunxi-with-spl.bin.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Simon Glass
643ad899f5 dm: sunxi: dts: Add sun7i device tree files
These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small
portion of these, but we may as well have something to look forward to.

The total compiled size is about 25KB.

Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Przemyslaw Marczak
6bc98f50e5 odroid: dts: fix name of included dtsi
Odroid is based on Exynos4412.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-27 19:21:08 -06:00
Przemyslaw Marczak
b746454903 odroid: dts: adjust sd cd-gpios for SD Card
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-27 19:21:08 -06:00
Przemyslaw Marczak
6a5ce1e906 trats2: dts: adjust gpio numbers after gpio rework
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-27 19:21:08 -06:00
Przemyslaw Marczak
265634701c trats: dts: adjust gpio numbers to new api
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-27 19:21:08 -06:00