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468 commits

Author SHA1 Message Date
Tirumala R Marri
5d4b3d2b31 ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fix
During recent PCI-E tests it has been found that current
driverl level and de-emphasis values are not set correctly.
After sweeping throgh all de-ephasis values, it was found that
0x130 is a right value. Where 0x13 is driver level and 0 is
de-emphasis.

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-22 10:31:41 +02:00
Stefan Roese
f556483734 ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patch
This patch fixes some minor issues introduced with the patch:
ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika:

- Rework memory-queue and PLB arbiter optimization code, that the
  local variable is not needed anymore. This removes one #ifdef.
- Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead
  of XXX+ 0x01). This was not introduced by Prodyut, just a
  copy-paste problem.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-21 11:05:03 +02:00
Prodyut Hazarika
079589bcfb ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-21 10:31:16 +02:00
Kumar Gala
ba37aa0328 fdt: rework fdt_fixup_ethernet() to use env instead of bd_t
Move to using the environment variables 'ethaddr', 'eth1addr', etc..
instead of bd->bi_enetaddr, bi_enet1addr, etc.

This makes the code a bit more flexible to the number of ethernet
interfaces.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-21 02:07:43 +02:00
Wolfgang Denk
2fd0aad443 Merge branch 'Makefile' of git://git.denx.de/u-boot-arm 2008-08-13 23:23:13 +02:00
Stefan Roese
5a7ddf4e1f Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-08-13 06:47:12 +02:00
Jean-Christophe PLAGNIOL-VILLARD
cc4a0ceeac drivers/mtd/nand: Move conditional compilation to Makefile
rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-13 01:40:43 +02:00
Stefan Roese
3df2ece0f0 NAND: Update 4xx NDFC driver to match updated nand subsystem
This patch changes the 4xx NAND driver ndfc.c to match the new
infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.

Tested successfully on AMCC Sequoia and Bamboo.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-12 11:31:23 -05:00
William Juul
5e1dae5c3d Fixing coding style issues
- Fixing leading white spaces
 - Fixing indentation where 4 spaces are used instead of tab
 - Removing C++ comments (//), wherever I introduced them

Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:17 -05:00
William Juul
cfa460adfd Update MTD to that of Linux 2.6.22.1
A lot changed in the Linux MTD code, since it was last ported from
Linux to U-Boot. This patch takes U-Boot NAND support to the level
of Linux 2.6.22.1 and will enable support for very large NAND devices
(4KB pages) and ease the compatibility between U-Boot and Linux
filesystems.

This patch is tested on two custom boards with PPC and ARM
processors running YAFFS in U-Boot and Linux using gcc-4.1.2
cross compilers.

MAKEALL ppc/arm has some issues:
 * DOC/OneNand/nand_spl is not building (I have not tried porting
   these parts, and since I do not have any HW and I am not familiar
   with this code/HW I think its best left to someone else.)

Except for the issues mentioned above, I have ported all drivers
necessary to run MAKEALL ppc/arm without errors and warnings. Many
drivers were trivial to port, but some were not so trivial. The
following drivers must be examined carefully and maybe rewritten to
some degree:
 cpu/ppc4xx/ndfc.c
 cpu/arm926ejs/davinci/nand.c
 board/delta/nand.c
 board/zylonite/nand.c

Signed-off-by: William Juul <william.juul@tandberg.com>
Signed-off-by: Stig Olsen <stig.olsen@tandberg.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:15 -05:00
Stefan Roese
f2302d4430 Fix merge problems
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-06 14:05:38 +02:00
Stefan Roese
66fe183b1d ppc4xx: Fix incorrect MODTx setup for some DIMM configurations
This patch fixes a problem with incorrect MODTx (On Die Termination)
setup for a configuration with multiple DIMM's and multiple ranks.
Without this change Katmai was unable to boot Linux with DDR2 frequency
>= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux
with DDR2 frequency = 640MHz and mem=4GB.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-18 15:57:23 +02:00
Stefan Roese
60204d06ed ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-18 12:31:25 +02:00
Ricardo Ribalda Delgado
d865fd0980 ppc4xx: CPU PPC440x5 on Virtex5 FX
-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>
2008-07-18 12:30:50 +02:00
Stefan Roese
42246dacf6 Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next 2008-07-17 10:41:06 +02:00
Wolfgang Denk
d0ff51ba5d Code cleanup: fix old style assignment ambiguities like "=-" etc.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-07-14 15:19:07 +02:00
Stefan Roese
4b326101d6 Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next 2008-07-14 10:45:47 +02:00
Stefan Roese
068c1b77c8 ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-13 15:04:11 +02:00
Stefan Roese
b578fb4714 ppc4xx: Fix include sequence in 4xx_pcie.c
This patch now moves common.h to the top of the inlcude list. This
is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that
the phys_size_t/phys_addr_t are defined to the correct size in this
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 15:07:23 +02:00
Stefan Roese
69e2c6d0d1 ppc4xx: Fix compile warning in 44x_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
5de851403b ppc4xx: Rework 440GX UIC handling
This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.

Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
d1631fe1a0 ppc4xx: Consolidate PPC4xx UIC defines
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
4fb25a3db3 ppc4xx: Consolidate PPC4xx UIC defines
This patch is the first step to consolidate the UIC related defines in the
4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to
asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next
steps.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Stefan Roese
e321801bed ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards
This patch removes some ft_board_setup() functions from some 4xx boards.
This can be done since we now have a default weak implementation for this
in cpu/ppc4xx/fdt.c. Only board in need for a different/custom
implementation like canyonlands need their own version.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Stefan Roese
08250eb2ed ppc4xx: Fix merge problems in 44x_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Grant Erickson
1740c1bf40 ppc4xx: Add MII mode support to the EMAC RGMII Bridge
This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Grant Erickson
2e2050842e ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller
This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
controller registers (MODT and INITPLR) used by the
PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
peer values used for the INITPLR MR and EMR registers,
respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).

With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
Kilauea are replaced by equivalent mnemonics to make it easier to
compare and contrast other 405EX(r)-based boards (e.g. during board
bring-up).

Finally, unified the SDRAM controller register dump routine such that
it can be used across all processor variants that utilize the IBM DDR2
SDRAM controller core. It produces output of the form:

	PPC4xx IBM DDR2 Register Dump:
		...
	        SDRAM_MB0CF[40] = 0x00006701
		...

which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
since it is not uncommon that the DCR values in header files get mixed
up and it helps to validate, at a glance, they match what is printed
in the user manual.

Tested on:
  AMCC Kilauea/Haleakala:
  - NFS Linux Boot: PASSED
  - NAND Linux Boot: PASSED

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Feng Kan
7d30793685 ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.
Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:12 +02:00
Stefan Roese
b002144e1d ppc4xx: Fix printf format warnings now visible with the updated format check
This patch fixes ppc4xx related printf format warning. Those warnings are
now visible since patch dc4b0b38d4
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-10 09:58:06 +02:00
Stefan Roese
5d812b8b4a ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.

Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-10 09:14:01 +02:00
Stefan Roese
7c6237b3e2 Merge branch 'master' of /home/stefan/git/u-boot/u-boot 2008-07-07 09:51:25 +02:00
Michal Simek
9fea65a6c4 ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405
This change helps with better handling with others
Xilinx based platform.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Stefan Roese <sr@denx.de>
2008-07-06 22:39:14 +02:00
Stefan Roese
dd1c5523d6 ppc4xx: Fix 460EX/GT PCIe port initialization
This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was
configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing
this out.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-01 17:03:19 +02:00
Stefan Roese
745d8a0d3c ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic
This patch implements a fix provided by AMCC so that the lockup upon
simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur
anymore:

Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2]
(bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG,
USB 2.0 host and SATA.

This errata is not officially available yet. I'll update the comment
to add the errata number later.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-30 15:20:41 +02:00
Stefan Roese
aac7a5095b ppc4xx: Fix problem in gpio_config()
As pointed out by Guennadi Liakhovetski (thanks), pin2 is already shifted
left by one. So the additional shift is bogus.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-23 11:15:09 +02:00
Becky Bruce
9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Stefan Roese
b2815f7928 ppc4xx: Fix misspelled CONFIG_440SPE/440EPX/GRX config options
We use upper case letters for the AMCC processor defines (like
CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and
not CONFIG_440SPe. This patch fixes the last misspelled config options.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-06 16:10:41 +02:00
Stefan Roese
bbeff30cbd ppc4xx: Remove superfluous dram_init() call or replace it by initdram()
Historically the 405 U-Boot port had a dram_init() call in early init
stage. This function was still called from start.S and most of the time
coded in assembler. This is not needed anymore (since a long time) and
boards should implement the common initdram() function in C instead.

This patch now removed the dram_init() call from start.S and removes the
empty implementations that are scattered through most of the 405 board
ports. Some older board ports really implement this dram_init() though.
These are:

csb272
csb472
ERIC
EXBITGEN
W7OLMC
W7OLMG

I changed those boards to call this assembler dram_init() function now
from their board specific initdram() instead. This *should* work, but please
test again on those platforms. And it is perhaps a good idea that those
boards use some common 405 SDRAM initialization code from cpu/ppc4xx at
some time. So further patches welcome here.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:22:19 +02:00
Stefan Roese
192f90e272 ppc4xx: Use new 4xx SDRAM controller enable defines in common ECC code
Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:22:13 +02:00
Stefan Roese
39b32be18c ppc4xx: Fix common ECC generation code for 440GP style platforms
This patch makes the common 4xx ECC code really usable on 440GP style
platforms.

Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
we need to make some processor dependant defines used later on by the
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:22:08 +02:00
Stefan Roese
ec724f883e ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.

Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:22:03 +02:00
Stefan Roese
36ea16f6a0 ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1
This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).

It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:

used on 405GR/CR/EP and some Xilinx Virtex boards.

used on 440GP/GX/EP/GR.

used on 440EPx/GRx.

used on 405EX/r/440SP/SPe/460EX/GT.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:21:53 +02:00
Stefan Roese
64852d09e0 ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S
This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.

Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2008-06-03 20:21:49 +02:00
Grant Erickson
c821b5f120 ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling
This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
    Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:20:50 +02:00
Grant Erickson
a439680019 PPC4xx: Simplified post_word_{load, store}
This patch simplifies post_word_{load,store} by using the preprocessor
to eliminate redundant, copy-and-pasted code.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
2008-06-03 20:20:01 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Stefan Roese
70fab1908f ppc4xx: Add 405EX(r) revision C PVR definitions and detection code
Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-13 20:22:01 +02:00
Stefan Roese
cb5d88b961 ppc4xx: Add weak default ft_board_setup() routine
This patch adds a default ft_board_setup() routine to the 4xx fdt code.
This routine is defined as weak and can be overwritten by a board specific
one if needed.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-08 11:01:09 +02:00
Dave Mitchell
b9bbefce1a ppc4xx: Fix typos in 460GT/EX FBDV array
Corrected two typos in the 460GT/EX FBDV array.

Signed-off-by: Dave Mitchell <dmitchell@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-08 07:01:41 +02:00
Stefan Roese
ea9202a659 ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.c
This patch fixes a problem with DIMMs that have 8 banks. Now the
MCIF0_MBxCF register will be setup correctly for this setup too.

This was noticed with the 512MB DIMM on Canyonlands/Glacier.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-30 14:50:04 +02:00
Stefan Roese
cab99d6f32 ppc4xx: Fix compilation warning in denali_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-29 14:44:54 +02:00
Stefan Roese
85ad184b3b ppc4xx: Complete remove bogus dflush()
Since the current dflush() implementation is know to have some problems
(as seem on lwmon5 ECC init) this patch removes it completely and replaces
it by using clean_dcache_range().

Tested on Katmai with ECC DIMM.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-29 13:57:07 +02:00
Markus Brunner
eea5a743a2 ppc4xx: Fixup ebc clock in FDT for 405GP/EP
On ppc405EP and ppc405GP (at least) the ebc is directly attached to the plb
and not to the opb. This patch will try to fixup /plb/ebc if /plb/opb/ebc
doesn't exist.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
2008-04-29 07:37:54 +02:00
Wolfgang Denk
1d907e66fd Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx 2008-04-26 00:06:13 +02:00
Wolfgang Denk
d00ce09040 USB: fix more GCC 4.2.x aliasing warnings
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Markus Klotzbuecher <mk@denx.de>
2008-04-25 12:44:08 +02:00
Stefan Roese
24bfedbd0b ppc4xx: Pass PCIe root-complex/endpoint configuration to Linux via the fdt
The PCIe root-complex/endpoint setup as configured via the "pcie_mode"
environment variable will now get passed to the Linux kernel by setting
the device_type property of the PCIe device tree node. For normal root-
complex configuration it will keep its defaults value of "pci" and for
endpoint configuration it will get changed to "pci-endpoint".

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-25 11:44:47 +02:00
Stefan Roese
8deafdc6ad ppc4xx: Add dcache_enable() for 440
dcache_enable() was missing for 440 and the patch
017e9b7925 ["allow ports to override bootelf
"] behavior uses this function.

Note: Currently the cache handling functions like
d/icache_disable/enable() are NOP's on 440. This may be changed in the
future.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-22 12:26:33 +02:00
Matthias Fuchs
e1d09680f6 ppc4xx: Fix sys_get_info() for 405GP(r)
This patch assigns the correct EBC clock for 405GP(r) CPUs
to PPC4xx_SYS_INFO structure. Without this patch U-Boot
uses an uninitialized EBC clock in its startup message.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-04-21 06:54:08 +02:00
Anatolij Gustschin
5e3dca577b Fix crash on sequoia in ppc_4xx_eth_init
Currently U-Boot crashes in ppc_4xx_eth_init on sequoia
with cache enabled (TLB Parity exeption). This patch
fixes the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-04-18 00:48:27 -07:00
Anatolij Gustschin
accf735576 ppc4xx: Fix crash on sequoia with cache enabled
Currently U-Boot crashes on sequoia board in CPU POST if
cache is enabled (CONFIG_4xx_DCACHE defined). The cache
won't be disabled by change_tlb before CPU POST because
there is an insufficient adress range check since
CFG_MEM_TOP_HIDE was introduced. This patch tries to fix
this problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-04-18 00:48:02 -07:00
Stefan Roese
e54ec0f016 ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3
This patch fixes a problem with the RGMII setup of the 460GT. The 460GT
has 2 RGMII instances and we need to configure the 2nd RGMII instance
for the EMAC2+3 channels.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-03 14:50:34 +02:00
Larry Johnson
eb14ebe813 ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-03-31 12:20:59 +02:00
Markus Brunner
f766cdf89b ppc4xx: PPC405EP Set EMAC noise filter bits
This bug was introduced with commit aee747f19b
which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.

Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 10:47:28 +01:00
Mike Nuss
f66e2c8b25 ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
after startup to change the speed of the clocks. This patch adds the
option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
initialization code will reconfigure the PLL to run the system with a CPU
frequency of 667MHz and PLB frequency of 166MHz, without the need for an
external EEPROM.

Signed-off-by: Mike Nuss <mike@terascala.com>
Acked-by: Stefan Roese <sr@denx.de>
2008-03-27 10:38:54 +01:00
Stefan Roese
9ad31989de ppc4xx: Fix compilation warning in 4xx_enet.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Stefan Roese
4c9e855734 ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Stefan Roese
d8bd643141 ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clear
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:03 +01:00
Stefan Roese
71665ebf88 ppc4xx: Add Canyonlands NAND booting support
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.

This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.

Tested with 512 byte page NAND device (32MByte) on Canyonlands.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:05 +01:00
Stefan Roese
2801b2d2a9 ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:04 +01:00
Stefan Roese
8ac41e3e37 ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Stefan Roese
56e4101783 ppc4xx: interrupt.c reworked
This patch is a rework of the 4xx interrupt handling done while
adding the 460EX/GT support. Interrupts are needed on 4xx for the
EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Stefan Roese
84a999b6cd ppc4xx: program_tlb now uses 64bit physical addess
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Stefan Roese
c3307fa186 ppc4xx: miiphy.c reworked
While adding the 460EX/GT support I reworked the 4xx miiphy code. It
badly neede some cleanup.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:03 +01:00
Mike Nuss
74eb022259 PPC4xx (Sequoia): Fix Ethernet "remote fault" problems
Every now and then a Sequoia board (or equivalent hardware) had
problems connecting to a Gigabit capable network interface.

There were differences in the PHY setup between Linux and U-Boot.

This patch fixes the problem. Apparently "remote fault" is being set,
which signals to some devices (on the other end of the cable) that a
fault has occurred, while other devices ignore it. I believe the RF bit
was causing the issue, but I removed T4 also, to match up with Linux.

Signed-off-by: Mike Nuss <mike@terascala.com>
2008-03-04 08:55:27 +01:00
Stefan Roese
76957cb3d6 ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But
currently 4k/2k is configured. This patch fixes this issue.

Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-02 22:49:27 +01:00
Anatolij Gustschin
4fae35a53b ppc4xx: Fix problem in 4xx_enet.c driver
U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is
enabled. To reproduce the problem ensure that 'ethrotate'
environment variable isn't set to "no" and then run
"tftp 200000 not_existent_file".
This patch tries to fix the issue.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-03-02 21:34:55 +01:00
Shinya Kuribayashi
495a0dde7f cpu/ppc4xx/config.mk: Make a needlessly deffered expansion immediate.
This will reduce the build time.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
2008-02-23 09:44:54 +01:00
Wolfgang Denk
32c70d3420 Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx 2008-02-15 00:22:37 +01:00
Wolfgang Denk
e7670f6c1e PPC: Use r2 instead of r29 as global data pointer
R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc
will refuse to use load/store multiple insns; instead, it issues a
list of simple load/store instructions upon function entry and exit,
resulting in bigger code size, which in turn makes the build for a
few boards fail.

Use r2 instead.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-02-14 22:43:22 +01:00
Rafal Jaworowski
f57d7d364c ppc: Refactor cache routines, so there is only one common set.
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-02-14 22:00:41 +01:00
Larry Johnson
29e3500cbc ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-02-14 07:42:32 +01:00
Stefan Roese
ff02f13980 ppc4xx: Fix ndfc HW ECC byte order
The current ndfc HW ECC implementation swaps the first two ECC bytes.
But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering,
so this swapping in the HW ECC driver is bogus. This patch fixes this
problem and now really uses the SMC ECC byte order.

Thanks to Sean MacLennan for pointing this out.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-02-04 11:47:40 +01:00
Stefan Roese
28d77d968b ppc4xx: Fix problem with init-ram bigger than 4k on 440 platforms
Signed-off-by: Stefan Roese <sr@denx.de>
2008-02-04 11:47:40 +01:00
Stefan Roese
9adfc9fb9a ppc4xx: Remove compiler warning in cpu/ppc4xx/44x_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-15 10:11:02 +01:00
Larry Johnson
6d8184b00c ppc4xx: Fix dflush() to restore DVLIM register
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-10 18:53:16 +01:00
Marcel Ziswiler
7817cb2083 fix comments with new drivers organization
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2008-01-09 21:48:49 +01:00
Stefan Roese
1466ef8db5 Merge branch 'lwmon5-no-ocm' 2008-01-09 10:43:47 +01:00
Stefan Roese
1754f50b71 ppc4xx: Add CFG_POST_ALT_WORD_ADDR to support non OCM POST WORD storage
The privious 4xx POST implementation only supported storing the POST
WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer
we need to store the POST WORD in some other non volatile location.
This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such
a location.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-09 10:25:46 +01:00
Stefan Roese
e02c521d94 ppc4xx: Add 44x cache locking to better support init-ram in d-cache
This patch adds support for locking the init-ram/stack in d-cache,
so that other regions may use d-cache as well

Note, that this current implementation locks exactly 4k of d-cache,
so please make sure that you don't define a bigger init-ram area. Take
a look at the lwmon5 440EPx implementation as a reference.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-09 10:23:16 +01:00
Matthias Fuchs
6e9233d30a ppc4xx: Move cpu/ppc4xx/vecnum.h into include path
This patch allows the use of 4xx interrupt vector number defines
in board specific code outside cpu/ppc4xx.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-01-09 06:32:58 +01:00
Matthias Fuchs
580d1d3186 ppc4xx: Fix UIC2 vector number base
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2008-01-09 06:32:54 +01:00
Stefan Roese
802b769bac ppc4xx: Return 0 on success in 4xx ethernet driver
Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-08 18:39:30 +01:00
Larry Johnson
e05329516a ppc4xx: Remove weak binding from common Denali data-eye search code
Now that there are no board-specific versions of
"denali_core_search_data_eye()", the weak binding on the common version
can be removed.

Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-05 10:14:56 +01:00
Stefan Roese
6399b23d60 Merge branch 'katmai-ddr-gda' 2008-01-05 10:13:40 +01:00
Stefan Roese
5ba576c016 ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-05 09:13:46 +01:00
Stefan Roese
845c6c95db ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-05 09:12:41 +01:00
Lawrence R. Johnson
5ab884b254 ppc4xx: Add functionality to GPIO support
This patch makes two additions to GPIO support:

First, it adds function gpio_read_in_bit() to read the a bit from the
GPIO Input Register (GPIOx_IR) in the same way that function
gpio_read_out_bit() reads a bit from the GPIO Output Register
(GPIOx_OR).

Second, it modifies function gpio_set_chip_configuration() to provide
an additional option for configuring the GPIO from the
"CFG_4xx_GPIO_TABLE".

According to the 440EPx User's Manual, when an alternate output is used,
the three-state control is configured in one of two ways, depending on
the particular output.  The first option is to select the corresponding
alternate three-state control in the GPIOx_TRSH/L registers.  The second
option is to select the GPIO Three-State Control Register (GPIOx_TCR) in
the GPIOx_TRSH/L registers, and set the corresponding bit in the
GPIOx_TCR register to enable the output.  For example, the Manual
specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use
the alternate three-state control (first option), and specifies
configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output
enabled in the GPIOx_TCR register (second option).

Currently, gpio_set_chip_configuration() configures all alternate signal
outputs to use the first option.  This patch allow the second option to
be selected by setting the "out_val" element in the table entry to
"GPIO_OUT_1".  The first option is used when the "out_val" element is
set to "GPIO_OUT_0".  Because "out_val" is not currently used when an
alternate signal is selected, and because all current GPIO tables set
"out_val" to "GPIO_OUT_0" for all alternate signals, this patch should
not change any existing configurations.

Signed-off-by: Larry Johnson <lrj@acm.org>
2008-01-04 11:38:45 +01:00
Stefan Roese
c05569066d ppc4xx: Enable 405EP PCI arbiter per default on all boards
In an attmemt to clean up the 4xx start.S file, I removed the enabling
of the internal 405EP PCI arbiter. This is needed for multiple other
405EP platforms, like most of the esd 405EP. Now the internal PCI
arbiter is enabled again per default as it has been before.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-12-28 16:39:15 +01:00
Stefan Roese
bec9264616 ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-12-28 16:39:11 +01:00
Larry Johnson
8eb52d5d98 Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx Makefile
Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:36 +01:00