As reported by Simon Guinot, commit ade741b3
"arm: mvebu: Call timer_init early before PHY and DDR init" breaks
Kirkwood platforms. As the static variable "init_done" is not
available at that early boot time. This patch moves it to explicitly
to the data section, making it available at that time.
Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Simon Guinot <simon.guinot@sequanux.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Currently booting on A38x is broken. As the current code tries to detect
the SoC family to disable the MMU for the A38x at runtime. But before the
internal registers are switched to the new location (0xf100.0000), this
runtime detection does not work. As all macros / defines are already
assigned to the new location at 0xf100.0000. But the registers are sill
mapped to the default location at 0xd000.0000.
This patch now makes sure, no such runtime detection is used before
the internal registers are configured to the new location. After this,
the remaining cache cleanup is executed.
Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Use DM for the pl01x serial driver on hikey. Also allow UART0 or
UART3 to be chosen via Kconfig.
By default we now output to UART3 as the latest version of ATF outputs
to this UART. Also UART3 comes out on the LS connector, as opposed to
UART0 which goes to a unpopulated header.
As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and
call the pinmux configuration code for the UART. Before we were
relying on ATF having already configured the pin configuration.
NB: Upstream Linux kernel doesn't yet support UART3, so serial console
will still be output on UART0 when booting a upstream kernel.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Most platforms enable these options from Kconfig rather
than the configs header file.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Currently, the USB boot mode is supported by an external loader and
U-boot proper image is put on the section 0. This commit allows
access there.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move init code of low-level debug into a single file.
This is helpful to create an image that runs on multiple SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, IECTRL is enabled after pin-mux settings for the low-level
debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input
signals are pulled-down, i.e. glitch signal (Low to High transition)
problem occurs if pin-mux is set up first. As a result, one invalid
character is input to the UART block and the auto-boot counting is
terminated immediately.
The correct initialization procedure is:
[1] Enable IECTRL (if IECTRL exists for the pins)
[2] Set up pin-muxing
[3] Deassert the reset of the hardware block
Currently, the low-level debugging is working for PH1-sLD3 and
PH1-Pro4, but just in case, follow the sequence for all the SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros. Also, rename the C file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The macro, led_write(), is now only used in C sources. There is no
more reason to keep the tricky assembly macro. Replace it with a
new C function led_puts().
Also, rename board.h to micro-support-card.h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The wrapper functions, uniphier_board_*, are just making function
calls complex. Remove them.
Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Device tree specifies the available memory ranges in its "/memory"
node. Use it to simplify the CONFIG defines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
0x00000000 - 0x0fffffff
0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.
In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.
Going forward, use the latter for the external bus.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards. It has been painful to maintain
both. Having one of them is enough.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These input enable settings are handled by the pinctrl drivers.
Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add "u-boot,dm-pre-reloc" for device nodes we want in SPL DTB
(spl/u-boot-spl.dtb).
The "soc" node (this is simple-bus node) also needs the property
to bind the pinctrl node located under it.
I am collecting this U-Boot specific hack to the bottom of board
DTS rather than inserting "u-boot,dm-pre-reloc" into SoC DTSI.
My goal is to sync DTSI with Linux for easier maintenance.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Some i.MXes use __NA_ or 0 to avoid setting mux_mode, but the following patch
only take i.MX6/7 into consideration.
"c3c8a5748897b24f18618047804317167a531dd3 imx-common: fix iomux settings"
Use is_soc_type(MXC_CPU_MX7) to avoid breaking other i.MXes when
setting mux_mode.
In this patch, switch to use "asm/imx-common/sys_proto.h" to avoid
build break for "is_soc_type" for vf610 and mx25.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and
socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA
board config files.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
When setting iomux for a pin mux, there is no need to check mux_ctrl_ofs.
Also If still checking mux_ctrl_ofs, we have no chance to set iomux
for i.MX7D IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00, because the mux_ctrl_ofs
for this register is 0.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence"). The Tegra114 TRM doesn't contain this information, but
the programming of PLLC is the same on Tegra114 and Tegra124.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enabling a PLL while IDDQ is high. The Linux kernel checks for this
condition and warns about it verbosely, so while this seems to work
fine, fix it up according to the programming guidelines provided in
the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add the device tree node for the SPI controllers found on Tegra20 SOCs.
Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
While clk_m and the oscillator run at the same frequencies on Tegra114
and Tegra124, clk_m is the proper source for the architected timer. On
more recent Tegra generations, Tegra210 and later, both the oscillator
and clk_m can run at different frequencies. clk_m will be divided down
from the oscillator.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On currently supported SoCs, clk_m always runs at the same frequency as
the oscillator input. However newer SoC generations such as Tegra210 no
longer have that restriction. Prepare for that by separating clk_m from
the oscillator clock and allow SoC code to override the clk_m rate.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
AFAIK, for all PLLs on all Tegra SoCs, the primary PLL output frequency
is (input * m) / (n * p). However, PLLP's primary output (pllP_out0) on
T210 is the VCO output, and divp is not applied. pllP_out2 does have divp
applied. All other pllP_outN are divided down from pllP_out0. We only
support pllP_out0 in U-Boot at the time of writing.
Fix clock_get_rate() to handle this special case.
This corrects the returned rate for PLLP to be 408MHz rather than 204MHz.
In turn, this causes high enough dividers to be calculated for the various
peripheral clocks that feed off of PLLP. Without this, some peripherals
failed to operate correctly. For instance, one of my SD cards worked
perfectly but an older (presumably slower) card could not be read.
Note that prior to commit 722e000ccd "Tegra: PLL: use per-SoC pllinfo
table instead of PLL_DIVM/N/P, etc.", the calculated PLL frequency was
816MHz since the wrong values were being extracted from the PLLP divider
register. This caused overly large peripheral dividers to be calculated,
which while wrong, didn't cause any correctness issues; things simply ran
slower than they could.
Reported-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This function is deleted by commit 2fccd2d96b
"tegra: Convert tegra GPIO driver to use driver model".
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
two GPIO expansion headers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Commit 0abdd9d0 "arm: Remove nhk8815 boards and nomadik arch" missed one
reference to this arch. Lets remove this as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.
Please note that this patch also removes these config options:
- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.
If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
