Commit graph

33574 commits

Author SHA1 Message Date
Nishanth Menon
3df0b8b4da remoteproc: Introduce a sandbox dummy driver
Introduce a dummy driver for sandbox that allows us to verify basic
functionality. This is not meant to do anything functional - but is
more or less meant as a framework plumbing debug helper.

The sandbox remoteproc driver maintains absolutey no states and is a
simple driver which just is filled with empty hooks. Idea being to give
an approximate idea to implement own remoteproc driver using this as a
template.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-22 14:18:39 -04:00
Nishanth Menon
ddf56bc7e3 drivers: Introduce a simplified remoteproc framework
Many System on Chip(SoC) solutions are complex with multiple processors
on the same die dedicated to either general purpose of specialized
functions. Many examples do exist in today's SoCs from various vendors.
Typical examples are micro controllers such as an ARM M3/M0 doing a
offload of specific function such as event integration or power
management or controlling camera etc.

Traditionally, the responsibility of loading up such a processor with a
firmware and communication has been with a High Level Operating
System(HLOS) such as Linux. However, there exists classes of products
where Linux would need to expect services from such a processor or the
delay of Linux and operating system being able to load up such a
firmware is unacceptable.

To address these needs, we need some minimal capability to load such a
system and ensure it is started prior to an Operating System(Linux or
any other) is started up.

NOTE: This is NOT meant to be a solve-all solution, instead, it tries to
address certain class of SoCs and products that need such a solution.

A very simple model is introduced here as part of the initial support
that supports microcontrollers with internal memory (no MMU, no
execution from external memory, or specific image format needs). This
basic framework can then (hopefully) be extensible to other complex SoC
processor support as need be.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-22 14:18:38 -04:00
Mugunthan V N
0da3f2e695 defconfig: am335x: gp_evm: enable ethernet driver model
enable ethernet driver model for am335x gp evm as cpsw supports
driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:36 -04:00
Mugunthan V N
0c615e35aa defconfig: am335x: bbb: enable ethernet driver model
enable ethernet driver model for am335x beagle bone black as cpsw
supports driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:35 -04:00
Mugunthan V N
4cc77895eb drivers: net: cpsw: convert driver to adopt device driver model
adopt cpsw driver to device driver model

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-22 14:18:35 -04:00
Mugunthan V N
bcd5eedf8f drivers: net: cpsw: prepare driver for device model migration
prepare driver for device model migration

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-10-22 14:18:34 -04:00
Mugunthan V N
09bf4f2454 am335x_evm: do not define usb ether gadget when Eth DM is defined
Since usb ether gadget doesn't have support for driver model, so
not defining usb ether gadget when ethernet driver model is
defined.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:34 -04:00
Mugunthan V N
bd83e3df45 am335x_evm: prepare for eth driver model support
Prepare board file so that ethernet registration are
commented for DM conversion

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:33 -04:00
Sjoerd Simons
bc3199fd18 configs: am335x_evm: Support distro bootcmds
Add support for distro bootcmds and network booting while retaining
backwards compatibility with the current "legacy" setup. With these
changes the default boot sequence becomes:

* SD card (standard distro boot)
* SD card (legacy boot)
* EMMC (standard distro boot)
* EMMC (legacy boot)
* Nand (legacy boot)
* PXE (standard distro boot)
* DHCP (standard distro boot)

The older boot scripts have some overlap with what the distro
bootcommands to however i've left them unchanged to prevent introduction
of subtle bugs.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2015-10-22 14:18:33 -04:00
Sjoerd Simons
7749b67f6c configs: ti_armv7_common.h: Add default addresses for pxe and scripts
Add mandatory address variables for loading scripts and pxe configuration as
per README.distro

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
2015-10-22 14:18:32 -04:00
Sjoerd Simons
59d03cb377 config_distro_bootcmd.h: Use a private variable for bootpart
Hush has an oddity where using ${var} causes var to resolved in the the global
address space (iotw the environment) first and only afterwards will the local
variable space be searched.

This causes odd side-effects when iterating over the boot partitions
using ${bootpart} if the environment also has a bootpart variable (e.g. for
the various TI boards). Fix this by using the hopefully more unique
${distro_bootpart} instead of ${bootpart}.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2015-10-22 14:18:31 -04:00
Paul Kocialkowski
2da87ab353 omap-common: Common get_board_serial function to pass serial through ATAG
Since there is a common function to grab the serial number from the die id bits,
it makes sense have one to parse that serial number and feed it to the serial
ATAG.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:31 -04:00
Paul Kocialkowski
679f82c349 omap-common: Common function to display die id, replacing omap3-specific version
This introduces omap_die_id_display to display the full die id.
There is no need to store it in an environment variable, that no boot script
is using anyway.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:18:30 -04:00
Paul Kocialkowski
07815eb9f3 omap-common: Common serial and usbethaddr functions based on die id
Now that we have a common prototype to grab the omap die id, functions to figure
out a serial number and usb ethernet address can use it directly.
Those also get an omap_die_id prefix for better consistency.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:22 -04:00
Paul Kocialkowski
9fd5401659 omap5: omap_die_id support
This introduces omap5 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:21 -04:00
Paul Kocialkowski
987a40d52e omap4: omap_die_id support
This introduces omap4 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:20 -04:00
Paul Kocialkowski
b50a768528 omap3: omap_die_id support
This replaces the previous get_dieid definition with omap_die_id, that matches
the common omap_die_id definition.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:18 -04:00
Paul Kocialkowski
72931b15e7 omap-common: Common omap_die_id definition
This introduces a common definition for omap_die_id, that aims at providing a
common interface for accessing omap platform's die id bits.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-22 14:17:17 -04:00
dbatzle@dcbcyber.com
eda1dfafb3 ARM Fix pandaboard es and a4 revision ID
board_name environment variable was not getting set correctly for Pandaboard A4 and ES

Signed-off-by: David Batzle <dbatzle@dcbcyber.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>; Tom Rini <trini@ti.com>; Peter Robinson <pbrobinson@gmail.com>
2015-10-22 14:17:16 -04:00
Tom Rini
858dbdf841 Merge git://git.denx.de/u-boot-x86 2015-10-21 20:47:40 -04:00
George McCollister
e0ae64880b x86: Add support for Advantech SOM-6896
Advantech SOM-6896 is a Broadwell U based COM Express Compact Module
Type 6. This patch adds support for it as a coreboot payload.

On board SATA and SPI are functional. On board Ethernet isn't functional
but since it's optional and ties up a PCIe x4 that is otherwise brought
out, this isn't a concern at the moment. USB doesn't work since the
xHCI driver appears to be broken.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-10-21 16:29:27 -06:00
Bin Meng
3e45de6ed4 x86: ivybridge: Enable the MRC cache
This works correctly now, so enable it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Dropped malloc() and adjusted commit message:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:51 -06:00
Simon Glass
fd8f4729ac x86: ivybridge: Measure the MRC code execution time
This code takes about 450ms without the MRC cache and about 27ms with the
cache. Add a debug timer so that this time can be displayed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:51 -06:00
Simon Glass
e9b3967c0c x86: ivybridge: Fix car_uninit() to correctly set run state
At present a missing $ causes this code to hang when using the MRC cache/
Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:51 -06:00
Simon Glass
9fbc5ccd79 x86: ivybridge: Check the RTC return value
The RTC can fail, so check the return value for reads.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
53327d3e61 x86: ivybridge: Use 'ret' instead of 'rcode'
For consistency, use 'ret' to handle a return value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
9a4eb5977a dm: rtc: Correct rtc_read32() return value
The current check is incorrect and will fail when any non-zero byte is read.
Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
b26eb88658 rtc: mc146818: Use probe() to set up the device
At present this driver uses bind() to set up the device. The bind() method
should not touch the hardware, so move the init code to probe().

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:50 -06:00
Simon Glass
1bcb5c3a6c rtc: mc146818: Add a comment to the #endif
Add a comment to make it clear to which block the #endif relates.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
7b95252d82 x86: chromebook_link: Enable the debug UART
Add support for the debug UART on link. This is useful for early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
60994a02a5 x86: Init the debug UART if enabled
If the debug UART is enabled, get it ready for use at the earliest possible
opportunity. This is not actually very early, but until we have a stack it
is difficult to make it work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
c7fefcb912 debug_uart: Add an option to announce the debug UART
It is useful to see a message from the debug UART early during boot so that
you know things are working. Add an option to enable this. The message will
be displayed as soon as debug_uart_init() is called.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
0e977bc145 debug_uart: Support board-specific UART initialisation
Some boards need to set things up before the debug UART can be used. On
these boards a call to debug_uart_init() is insufficient. When this option
is enabled, the function board_debug_uart_init() will be called when
debug_uart_init() is called. You can put any code here that is needed to
set up the UART ready for use, such as set pin multiplexing or enable
clocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
Simon Glass
97b0597302 debug_uart: Adjust the declaration of debug_uart_init()
We want to be able to add other common code to this function. So change the
driver's version to have an underscore before it, just like
_debug_uart_putc(). Define debug_uart_init() to call this version.

Update all drivers to this new method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:50 -06:00
George McCollister
5ac98cb9bd x86: spi: Add support for Wildcat Point
Add the Wildcat Point ID so Broadwell U based boards can use SPI.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:27 -06:00
George McCollister
b6fa966dc0 x86: pci: Add PCI IDs for Wildcat Point
Add Wildcat Point AHCI and LPC PCI IDs which are present on Broadwell U
based (and possibly other) boards.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21 07:46:27 -06:00
Bin Meng
ef1683d5c3 x86: Pass correct cpu_index to ap_init()
In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten
by the ap_init() function address. Correct it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
06f16c4148 x86: galileo: Enable mrc cache
Now that we have added MRC cache on quark support codes,
enable it on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
2fc2b83a7d x86: quark: Implement mrc cache
Using existing mrccache library to implement mrc cache support
for Intel Quark.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
c6c80d8b3e x86: ivybridge: Correct two typos for MRC
It should be MRC, not MCR.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ec73da82a6 x86: Remove unused rw-mrc-cache properties in the link and panther dts files
"type" and "wipe-value" are never used by the mrccache codes.
Remove them to avoid confusion. This also removes the alignment
comment in the panther dts file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
74e56d1953 x86: baytrail: Issue full system reset in reset_cpu()
With MRC cache enabled, when typing 'reset' in the U-Boot shell,
BayTrail FSP initialization hangs at "Configuring Memory Start":

  Setting BootMode to 0
  Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56
  Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
  About to call MrcInit();
  BayleyBay Platform Type
  CurrentMrcData.BootMode = 4
  Taking Fastboot path!
  Configuring Memory Start...

Changing reset_cpu() to do a full system reset fixes this issue.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
638a058941 x86: Enable mrc cache for bayleybay and minnowmax
Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).

Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
8b185041a9 x86: baytrail: Save mrc cache to spi flash
Save MRC cache to SPI flash in arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ff1e18af9d x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()
fsp_init() call has a parameter nvs_buf which is used by FSP as the
MRC cache but currently is blindly set to NULL. Retreive the MRC
cache from SPI flash and pass it to fsp_init() call. After the call,
save FSP produced MRC cache to SPI flash too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
4b9f6a669e x86: Use struct mrc_region to describe a mrc region
Currently struct fmap_entry is used to describe a mrc region.
However this structure contains some other fields that are not
related to mrc cache and causes confusion. Besides, it does not
include a base address field to store SPI flash's base address.
Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to
calculate the SPI flash base address, which unfortunately is
not 100% correct as CONFIG_ROM_SIZE may not match the whole
SPI flash size.

Define a new struct mrc_region and use it instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
42913a1c7a x86: ivybridge: Use APIs provided in the mrccache lib
Remove the call to custom mrc cache APIs, and use the ones
provided in the mrccache lib.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
ed800961a0 x86: Add more common routines to manipulate mrc cache
This adds mrccache_reserve(), mrccache_get_region() and
mrccache_save() APIs to the mrccache codes. They are ported
from the ivybridge implementation, but with some changes.
For example, in the mrccache_reserve(), ivybridge version
only reserves the pure MRC data, which causes additional
malloc() when saving the cache as the save API needs some
meta data. Now we change it to save the whole MRC date plus
the meta data to elinimate the need for the malloc() later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
bfa95c538b x86: Add various minor tidy-ups in mrccache codes
Fix some nits, improve some comments and reorder some codes
a little bit.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:27 -06:00
Bin Meng
2fe66dbcbc x86: Do sanity test on the cache record in mrccache_update()
For the cache record to write in mrccache_update(), we should
perform a sanity test to see if it is a valid one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:26 -06:00