Device paths may consist of multiple instances. Up to now we have only
considered the size of the first instance. For the services of the
EFI_DEVICE_PATH_UTILITIES_PROTOCOL in most cases the total length of the
device path is relevant.
So let's rename efi_dp_size() to efi_dp_instance_size() and create a new
function efi_dp_size() that calculates the total device path length.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
efi_dp_size() is meant to return the device path length without the end
node.
The length of a device path containing only an end node was incorrectly
reported as 4.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
The logic of the AppendDevicePath service of the
EFI_DEVICE_PATH_UTILITIES_PROTOCOL is incorrectly implemented:
* if both paths are NULL an end node has to be returned
* if both paths are not NULL the end node of the second device path has to
be kept
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Implement the CreateDeviceNode service of the device path utility protocol.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Executing a test after failed setup may lead to unexpected behavior like
an illegal memory access. So after a setup failure we should skip to
teardown.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
We do not support bootefi booting ARMv7 in non-secure mode.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
According to the documentation the EFI log category is called LOGC_EFI.
All other categories start with LOGC_. So let's fix it.
Fixes: 1973b381a1 ("log: add category LOGC_EFI")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Currently, the address region, 0xf8000 - 0x100000, is used for SPL
stack for the 32bit SoCs. Because the U-Boot proper image starts
from 0x70000, the maximum size of the U-Boot proper image is 544KB
(0x70000 - 0xf8000) for the NOR boot mode. Now uniphier_v7_defconfig
is almost hitting this size limit. Changing CONFIG_SPL_STACK can
raise the size limit with less impact. With this, the size limit
will increase to 576KB (0x70000 - 0x100000). If we need to increase
it even more, we would be able to change CONFIG_SYS_UBOOT_BASE at the
cost of the flashing command changes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Some boards support an SD card and an eMMC device at the same time.
Since both belong to 'mmc', they are identified by a device number.
When the device number of the eMMC is 1 instead 0, "mmc dev" command
must be performed to switch the target device before flashing images.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The last clock consumer in SPL, SD/eMMC driver, gave up using the
clock driver. The clock driver is only used in U-Boot proper.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now that the SD/eMMC driver does not use the clock driver in SPL,
remove u-boot,dm-pre-reloc properties to let the fdtgrep tool drop
the unnecessary nodes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig.
When booting from SD/eMMC, obviously its clock has been properly set up
by the boot ROM. Acutually, no need to re-initialize the clock in SPL.
Using a clock driver would generalize the SoC specific code, but
solving the memory footprint problem would win.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I need to differentiate the clock handling for uniphier-sd. Move it
to each driver's probe function from the tmio common code so that
renesas-sdhi will not be affected.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
With the recent changes, the size of the U-Boot proper image for
uniphier_v7_defconfig exceeded the current limit, 512KB, then SPL
fails to load the whole of the U-Boot proper. Increase the size.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Odroid C2 fails to read from mmc with U-Boot v2018.03.
The change avoids a division by zero.
The fix was suggested by Jaehoon in
https://lists.denx.de/pipermail/u-boot/2018-January/318577.html
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Suggested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
In case of error in soc_clk_dump function are returned different values
then CMD return values (-1, 0, 1).
For example:
ZynqMP> clk dump
exit not allowed from main input shel
The patch is checking all negative return values and return
CMD_RET_FAILURE which is proper reaction for these cases.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Boards have an option to rewrite variable locations in their own board
files. This is necessary for qspi and nand configurations where boot
image can be bigger then 896k(current limit).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When static memory configuration is used U-Boot has capability to detect
memory size in setup range. Enable this feature for static
configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is no need to use zynq name as SYS_BOARD for all boards.
The patch is adding an option to change it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.
Also, we can mark zynq_nand_init() as static and get rid
of the mach-specific nand.h header.
This is really a revert of:
"mtd: zynq: nand: Move board_nand_init() function to board.c"
(sha1: 310995d9f9)
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This driver is currently broken, refusing to initialize properly.
The reason is that get_nand_dev_by_index() was being called before
nand_register(), thus returning a pointer into uninitialized memory.
In other words, the struct mtd_info used by the driver is total junk.
Fix it by getting the correct struct mtd_info, via nand_to_mtd()
on the driver's struct nand_chip.
Tested on a custom board, where the CPU is halted without this patch.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.
Fix that by inverting exit condition for readl_poll_timeout.
Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The disabled clk API returns -ENOSYS unlike the reset API returning -ENOTSUPP.
Fixes: ca7fdc8b12 ("usb: host: Add simple of glue driver for DWC3 USB Controllers integration")
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The E2 Silk port was broken since some time. This patch updates
the E2 Silk port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
NOTE: The port is missing support for I2C1 for DA9063 reset, since the
I2C driver needs to be converted to DM and DT probing. That's not
an issue for this patch though, since the reset was broken on Silk
since forever.
Add MMC DM and DT probing support into the SH MMCIF driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The initconst is not used in U-Boot, drop it. The r8a7794_crit_mod_clks
is also not used in U-Boot, so drop it too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The initconst is not used in U-Boot, drop it. The r8a7792_crit_mod_clks
is also not used in U-Boot, so drop it too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add clock control for ethernet controller on each SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Subtle ARC fixes for v2018.05-RC3
These are only very subtle clean-ups here and there including:
* Correctly specified CPU freq for HSDK
(production boards are all shipped with 500MHZ as opposed
to early batch running at 1GHz)
* Addition of SNPS internal group email to MAINTAINERS file
* Switch to Hush shell on AXS10x boards
In the commit "reset: Add get/assert/deassert/release for bulk of reset signals"
the disabled reset_release_bulk() and reset_get_bulk() used the wrong
struct clk_bulk instead of struct reset_ctl_bulk.
Fixes: 0c28233903 ("reset: Add get/assert/deassert/release for bulk of reset signals")
Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
commit b4d956f6bc ("bootm: Align cache flush end address correctly")
aligns the end address of the cache flush operation to a cache-line size to
ensure lower-layers in the code accept the range provided and flush.
A similar action should be taken for the begin address of a cache flush
operation. The load address may not be aligned to a cache-line boundary, so
ensure the passed address is aligned.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reported-by: Breno Matheus Lima <brenomatheus@gmail.com>
Suggested-by: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
