Commit graph

50403 commits

Author SHA1 Message Date
Rick Chen
7215787c4e SPDX: Convert single license tags to Linux Kernel style
Fix license tags problem after apply patchs about
riscv: Enable efi_loader support.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
2018-05-29 14:44:21 +08:00
Rick Chen
6836adbe75 efi_loader: Enable RISC-V support
We have almost all pieces needed to support RISC-V UEFI binaries in place already.
The only missing piece are ELF relocations for runtime code and
data.

This patch adds respective support in the linker script and the runtime
relocation code. It also allows users to enable the EFI_LOADER configuration
switch on RISC-V platforms.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
0979f7ce1e riscv: nx25: Enable distro boot
Distro boot allows for a common boot path on systems that allow distributions
to easily boot from a default configuration.

This patch enables distro boot for the nx25-ae250. Hopefully this can serve
as a good example for new boards, so they enable it as well.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
2c6903fa7b distro: Extend with RISC-V defines
While we don't have UEFI naming conventions for RISC-V file paths yet,
we need to search for something. So let's copy the removable file paths
from the RISC-V edk2 port.

Also add the official VCI strings that contain the standardized RISC-V
architecture ID fields.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
89aea43642 efi_loader: Use EFI_CACHELINE_SIZE in the image loader too
We were using our EFI_CACHELINE_SIZE define only in the runtime service
code, but left the image loader to use plain CONFIG_SYS_CACHELINE_SIZE.

This patch moves EFI_CACHELINE_SIZE into efi_loader.h and converts
the image loader to use it.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
b66babda45 riscv: Add board_quiesce_devices stub
This patch adds an empty stub for board_quiesce_devices() which allows boards
to quiesce their devices before we boot into an OS in a platform agnostic way.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
493d1e88b6 riscv: Add EFI application infrastructure
The hello world binary and a few selftests require to build EFI target
binaries, not just the EFI host environment.

This patch adds all required files to generate an EFI binary for
RISC-V.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
6cc1a2af46 riscv: Enable function sections
The linker can remove sections that are never addressed, so it makes a lot
of sense to declare every function as an individual section.

This reduces the output U-Boot code size by ~30kb for me.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Alexander Graf
a7f99e5dd7 riscv: Add setjmp/longjmp code
To support efi_loader we need to have platform support for setjmp/longjmp.
Add it here.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29 14:43:12 +08:00
Kelvin Cheung
c3c8638804 add FIT data-position & data-offset property support
Add FIT data-position & data-offset property support for bootm,
which were already supported in SPL.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
2018-05-26 18:19:19 -04:00
Ley Foon Tan
ee038c58d5 malloc: Use malloc simple before malloc is fully initialized in memalign()
Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use
malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes
to align with the requested alignment.

The original memalign() function will access mchunkptr struct to adjust the
alignment if there is misalignment happen, but mchunkptr struct is not being
initialized before full malloc is initialized. This cause the system crash.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2018-05-26 18:19:19 -04:00
Patrice Chotard
635159a090 mmc: stm32_sdmmc2: Fix stm32_sdmmc2_start_cmd()
SDMMC_CMD_CPSMEN bit is wrongly check and set in
SDMMC_ARG register instead of SDMMC_CMD register.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:19 -04:00
Patrick Delaunay
7f7deb0c72 stm32mp1: use OTP to configure MAC address and serial number
Use OTP57 and 58 for MAC address
- OTP57 = MAC address  bits [31:0]
- OTP58 = MAC address  bit  [47:32] stored in OTP  LSB's

Use manufacture information in OTP13 to OTP15 to build unique
chip id saved in env variable "serial#"
(used for USB device enumeration)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
c3600e1f92 stm32mp1: add FUSE command support
Add support of fuse command (read/write/program/sense)
on bank 0 to access to BSEC SAFMEM (4096 OTP bits).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
19f589923a stm32mp1: add bsec driver
Add a MISC driver with read and write access to BSEC IP
(Boot and Security and OTP control)
- offset 0: shadowed values
- offset 0x80000000: OTP fuse box values (SAFMEM)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
de20e43794 stm32mp1: remove the second TAMP_BOOT_CONTEXT update
The register TAMP_BOOT_CONTEXT is already updated in
get_bootmode() in cpu.c and no need to be done
twice.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
320d266368 stm32mp1: Allow to activate CONFIG_DEBUG_UART
Add the needed information to enable the debug uart
to have printf before the serial driver probe
(so before probe for clock, pincontrol and reset drivers)

To enable the debug on uart 4 (default console):
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_STM32=y

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
bc709a41ca serial: stm32: Add setparity support
Add possibility to update the serial parity used.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:18 -04:00
Patrick Delaunay
eae4764f1a dm: serial: Add setparity
Implements serial setparity ops to allow uart parity change.
It allows to select ODD, EVEN or NONE parity.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:17 -04:00
Patrice Chotard
be1a6f775e serial: stm32: Fix bits defines name
Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and
USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets.
Sort defines by descendant order.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 18:19:17 -04:00
Patrick Delaunay
215c8bed12 serial: stm32: Add debug uart support
Add support for early debug printf, before the availability of
driver model and device tree support.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 18:19:17 -04:00
Radoslaw Pietrzyk
246a5e5fc2 ram: stm32_sdram: Adds stm32f429-disco fixes for HardFault at booting
- adds reading FMC swap setting from DTB to SDRAM driver
- sets FMC swap for stm32f429-disco board
- changes ram start address to 0x90000000

Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26 18:19:17 -04:00
Ramon Fried
b460b889e2 serial: serial_msm: added pinmux & config
Serial port configuration was missing from previous implementation.
It only worked because it was preconfigured by LK.
This patch configures the uart for 115200 8N1.
It also configures the pin mux for uart pins using DT bindings.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26 18:19:17 -04:00
Ramon Fried
9558ddab96 db410: added pinctrl node and serial bindings
Added TLMM pinctrl node for pin muxing & config.
Additionally, added a serial node for uart.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26 18:19:16 -04:00
Ramon Fried
ad97051b7f mach-snapdragon: Introduce pinctrl driver
This patch adds pinmux and pinctrl driver for TLMM
subsystem in snapdragon chipsets.
Currently, supporting only 8016, but implementation is
generic and 8096 can be added easily.

Driver is using the generic dt-bindings and doesn't
introduce any new bindings (yet).

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 18:19:16 -04:00
Ramon Fried
640dc34942 mach-snapdragon: Fix UART clock flow
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26 18:19:11 -04:00
Ramon Fried
7e5ad796bc serial: serial_msm: initialize uart only before relocation
The uart is already initialized prior to relocation,
reinitialization after relocation is unnecessary.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Ramon Fried
11d59fe537 serial: serial_msm: fail probe if settings clocks fails
Failure to set the clocks will causes data abort exception when
trying to write to AHB uart registers.
This patch ensures that we don't touch these registers if clock
setting failed.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Ramon Fried
ffada23ca7 db820c: set clk node to be probed before relocation
The clock and serial nodes are needed before relocation.
This patch ensures that the msm-serial driver will probe
and provide uart output before relocation.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Chris Packham
0ed34aa741 Remove CONFIG_MVGBE from config_whitelist.txt
Now that there are more boards defining this it can be removed from the
whitelist.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
5ce9aca8a6 PCI: Document pciauto_region_allocate()
Add a doc comment for pciauto_region_allocate().

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
d71975ae6e PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resources
Currently, if we happen to allocate an address requiring 64 bits to a
device only supporting 32-bit BARs, the address eventually gets silently
truncated to 32 bits. Avoid this by adding a new flag to
pciauto_region_allocate() to bail out in such situations.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
ed12a89d07 PCI: Add newlines to debug prints in pci_auto_common.c
All of the debug output from this file is squished to one line. Fix
it.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
9792be7d93 doc: qemu-arm: Drop highmem=off references
Now that U-Boot works fine with highmem enabled, there is no need to
tell users to disable highmem.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
f37770c770 ARM: qemu-arm: Bump RAM size in AArch64 MMU table
Now that PCI devices work with highmem-enabled QEMU emulation, bump up
the RAM size in the MMU tables to gain access to the full 255 GB of RAM
potential instead of the puny 3 GB.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Tuomas Tynkkynen
52ba907328 PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not set
Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with
the 'highmem=off' parameter passed to QEMU's virt machine. The reason is
that when 'highmem' is not disabled, QEMU appends 64-bit a memory
resource to the PCI controller's regions property in DT in addition to
the 32-bit PCI memory window in low memory. And the current DT parsing
code picks the last (thus the 64-bit one) memory resource, whose address
eventually gets silently truncated to 32 bits because
CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break.

Avoid this problem by ignoring memory regions whose addresses are above
the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set.

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26 12:46:50 -04:00
Miquel Raynal
2a8e80dfce configs: add TPMv2.x support in Sandbox
Enable the Sandbox TPMv2 driver in all possible configurations.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:01 -04:00
Miquel Raynal
b91ad16a69 sandbox: dts: add Sandbox TPMv2.x node
This node declares the presence of the Sandbox TPMv2.x emulated chip,
available for testing.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:00 -04:00
Miquel Raynal
31b106fc1c doc: device-tree-bindings: add Sandbox TPMv2.0 module info
Add Sandbox TPMv2.0 module bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:00 -04:00
Miquel Raynal
2bae712f7a tpm: add a Sandbox TPMv2.x driver
This driver can emulate all the basic functionalities of a TPMv2.x
chip and should behave like them during regular testing.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:00 -04:00
Miquel Raynal
2dffe1c6ad test/py: add TPMv2.x test suite
Add tests for the TPMv2.x commands.
These commands may run both on a physical TPM and with the sandbox
driver.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:13:00 -04:00
Miquel Raynal
8ee59472cb doc: device-tree-bindings: add TIS TPMv2.0 SPI module info
Add TIS TPMv2.0 SPI module bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:59 -04:00
Miquel Raynal
a174f0001f tpm2: tis_spi: add the possibility to reset the chip with a gpio
On some designs, the reset line could not be connected to the SoC reset
line, in this case, request the GPIO and ensure the chip gets reset.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-25 20:12:59 -04:00
Miquel Raynal
eb46910b4b tpm: add support for TPMv2.x SPI modules
Add the tpm2_tis_spi driver that should support any TPMv2 compliant
(SPI) module.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-25 20:12:59 -04:00
Miquel Raynal
b9dd4fabbe tpm: add PCR authentication commands support
Add support for the TPM2_PCR_SetAuthPolicy and
TPM2_PCR_SetAuthValue commands.

Change the command file and the help accordingly.

Note: These commands could not be tested because the TPMs available
do not support them, however they could be useful for someone else.
The user is warned by the command help.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:59 -04:00
Miquel Raynal
dc26e913a8 tpm: add TPM2_HierarchyChangeAuth command support
Add support for the TPM2_HierarchyChangeAuth command.

Change the command file and the help accordingly.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:58 -04:00
Miquel Raynal
da9c3392e6 tpm: add dictionary attack mitigation commands support
Add support for the TPM2_DictionaryAttackParameters and
TPM2_DictionaryAttackLockReset commands.

Change the command file and the help accordingly.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:58 -04:00
Miquel Raynal
69cd8f0681 tpm: add TPM2_GetCapability command support
Add support for the TPM2_GetCapability command.

Change the command file and the help accordingly.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:58 -04:00
Miquel Raynal
1c4ea8f496 tpm: add TPM2_PCR_Read command support
Add support for the TPM2_PCR_Read command.

Change the command file and the help accordingly.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:58 -04:00
Miquel Raynal
6284be5a90 tpm: add TPM2_PCR_Extend command support
Add support for the TPM2_PCR_Extend command.

Change the command file and the help accordingly.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25 20:12:57 -04:00