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mach-snapdragon: Fix UART clock flow

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UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
This commit is contained in:
Ramon Fried 2018-05-16 12:13:39 +03:00 committed by Tom Rini
parent 7e5ad796bc
commit 640dc34942
5 changed files with 43 additions and 12 deletions
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23
arch/arm/mach-snapdragon/clock-apq8016.c
View file

@ -17,7 +17,6 @@
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(17)
#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
static const struct bcr_regs sdc_regs[] = {
{
@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = {
}
};
static struct gpll0_ctrl gpll0_ctrl = {
static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
.vote_bit = BIT(0),
};
static struct vote_clk gcc_blsp1_ahb_clk = {
.cbcr_reg = BLSP1_AHB_CBCR,
.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
.vote_bit = BIT(10),
};
/* SDHCI */
@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
/* 800Mhz/div, gpll0 */
clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
CFG_CLK_SRC_GPLL0);
clk_enable_gpll0(priv->base, &gpll0_ctrl);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
return rate;
@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = {
/* UART: 115200 */
static int clk_init_uart(struct msm_clk_priv *priv)
{
/* Enable iface clk */
clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
/* Enable AHB clock */
clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
CFG_CLK_SRC_GPLL0);
clk_enable_gpll0(priv->base, &gpll0_ctrl);
/* Vote for gpll0 clock */
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
/* Enable core clk */
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);

4
arch/arm/mach-snapdragon/clock-apq8096.c
View file

@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = {
.D = SDCC2_D,
};
static const struct gpll0_ctrl gpll0_ctrl = {
static const struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
CFG_CLK_SRC_GPLL0);
clk_enable_gpll0(priv->base, &gpll0_ctrl);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
return rate;

17
arch/arm/mach-snapdragon/clock-snapdragon.c
View file

@ -30,7 +30,7 @@ void clk_enable_cbc(phys_addr_t cbcr)
;
}
void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
{
if (readl(base + gpll0->status) & gpll0->status_bit)
return; /* clock already enabled */
@ -41,6 +41,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
;
}
#define BRANCH_ON_VAL (0)
#define BRANCH_NOC_FSM_ON_VAL BIT(29)
#define BRANCH_CHECK_MASK GENMASK(31, 28)
void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
{
u32 val;
setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
do {
val = readl(base + vclk->cbcr_reg);
val &= BRANCH_CHECK_MASK;
} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
}
#define APPS_CMD_RGCR_UPDATE BIT(0)
/* Update clock command via CMD_RGCR */

10
arch/arm/mach-snapdragon/clock-snapdragon.h
View file

@ -11,13 +11,18 @@
#define CFG_CLK_SRC_GPLL0 (1 << 8)
#define CFG_CLK_SRC_MASK (7 << 8)
struct gpll0_ctrl {
struct pll_vote_clk {
uintptr_t status;
int status_bit;
uintptr_t ena_vote;
int vote_bit;
};
struct vote_clk {
uintptr_t cbcr_reg;
uintptr_t ena_vote;
int vote_bit;
};
struct bcr_regs {
uintptr_t cfg_rcgr;
uintptr_t cmd_rcgr;
@ -30,9 +35,10 @@ struct msm_clk_priv {
phys_addr_t base;
};
void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
void clk_enable_cbc(phys_addr_t cbcr);
void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source);

1
arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
View file

@ -13,6 +13,7 @@
/* Clocks: (from CLK_CTL_BASE) */
#define GPLL0_STATUS (0x2101C)
#define APCS_GPLL_ENA_VOTE (0x45000)
#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)