Add timer_get_boot_us() to support boards, that have CONFIG_BOOTSTAGE
enabled, like pogo_v4.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
This patch adds support for other Marvell Armada SoC's, supporting the
25MHz fixed clock operation, like the Armada XP etc.
Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Tony Dinh <mibodhi@gmail.com>
With the recent changes in the Marvel mvneta network driver, the MDIO
bus is not connected any more. This patch updates the DT nodes to use
the nodes from the dtsi files instead of creating ad-hoc nodes.
Signed-off-by: Stefan Roese <sr@denx.de>
- Remove EFI support as it's not used on this board
- Disable CONFIG_FIT_PRINT to reduce the serial output (minimal speedup)
Signed-off-by: Stefan Roese <sr@denx.de>
32-bit Marvell Armada BootROMs limit maximal size of SPL image to 192 kB.
So define 192 kB (= 0x30000) limit as default value for SPL_SIZE_LIMIT.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Maximal size of u-boot kwb image binary is $CONFIG_ENV_OFFSET which is
0xF0000 = 983040 bytes. So add missing CONFIG_BOARD_SIZE_LIMIT definition
to ensure that u-boot binary does not overflow to the u-boot env storage.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Currently CONFIG_BOARD_SIZE_LIMIT check is ignored for u-boot-spl.kwb
target. Fix it by adding missing $(BOARD_SIZE_CHECK) macro.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
commit 970bf8603b ("Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig")
had an unintended side effect of resulting in a bootcmd env var change
for boards like venice that did not have CONFIG_USE_BOOTCOMMAND defined
and relied on it being defaulted in include/config_distro_bootcmd.h.
Following that patch it instead got defaulted in tools/env/fw_env_private.h
Fix this by enabling CONFIG_USE_BOOTCOMMAND for venice.
Fixes: commit 970bf8603b ("Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
I messed up application of patch 5a428e7510 ("mmc: fsl_esdhc_spl: Add
support for builds without CONFIG_SYS_MMC_U_BOOT_OFFS"). I took it from
a work-in-progress branch where I changed usage of
CONFIG_SDCARD to CONFIG_SD_BOOT
and refactored
SYS_MPC85XX_NO_RESETVEC
mess.
But these changes aren't in master yet. Fix the wrong usage of these
macros.
Fixes: 5a428e7510 ("mmc: fsl_esdhc_spl: Add support for builds without
CONFIG_SYS_MMC_U_BOOT_OFFS")
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Pali Rohár <pali@kernel.org>
Previously, in order for the `pinctrl-*` DT node properties
to be properly processed, the pinctrl's subnodes were limited
to only having the `pinmux` property as well as other additional
properties (slew-rate, bias-disable, etc.). Now, with this patch
the pinctrl driver is made to work similarly to the one from Linux.
It can now distinguish between one subnode and a subnode with multiple
subnodes.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
This has been done in order to align the DT of U-Boot with the DT
of Linux. In Linux, a phandle from a '-gpio' DT property is linked
to the pinctrl driver, a single driver that handles both pinctrl
settings and offers GPIO API to callers. On the other hand,
U-Boot redirects such phandle to a corresponding UCLASS_GPIO
driver, because U-Boot offers two different types of drivers
in this case: UCLASS_PINCTRL which handles pin functions and
UCLASS_GPIO which handles gpio requests as a gpio provider.
Due to this, we have two drivers in Uboot, but the Devicetree
has a single node. Thus, just one of the drivers can be probed
for the DT node during platform initialization, before relocation.
Our previous solution in U-Boot was to have a different devicetree:
the gpio node has a subnode for the pinctrl driver, which
is not compliant with Linux ABI. Furthermore, our documentation
for this type of nodes mentions no such gpio compatible.
After this patch, we can no longer add nodes with a gpio
compatible in the DT. Thus, in order to link the pinctrl driver to
the gpio one, a hook to the bind method of the former in U-Boot has
been added and the GPIO related compatibles have been removed to
avoid conflict when compatibles are enumerated and bound to drivers
during platform start before relocation. The bind method will attach
the GPIO driver to the pinctrl DT node so that every phandle coming
from '-gpio' DT properties will be redirected to a valid driver
attached to the pinctrl DT node.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
This patch makes sure that the Devicetree for the sama7
boards are aligned with the Devicetree from Linux. This
implies removing the GPIO compatible and replacing it
with the PINCTRL one, as well as unifying the SDMMC
pinctrl related subnodes under one single subnode.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
This patch makes sure that the Devicetree for the sama5
boards are aligned with the Devicetree from Linux. This
implies removing the GPIO compatible and replacing it
with the PINCTRL one, as well as unifying the SDMMC
pinctrl related subnodes under one single subnode.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
ddrck and qspick should have mck_div as parent clocks to be in sync with
linux driver.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Call the PDA detection mechanism at boot time so that we can
have the pda environment variable ready for use.
Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
SAM9X60 SoC can have extra clip boards (PDAs) connected, which have
an EEPROM memory for identification. A special GPIO can be used to read
this memory over 1wire protocol. Enabling one wire and eeprom drivers
for this memory.
Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Whenever the SD Card would be removed and then re-inserted while in the
U-Boot command line, the `SDBPWR` bit of the `SDMMC_PCR` register would
remain unset afterwards. In order for the bit to be set again after
re-insertion, register an additional `deferred_probe` method that the
DM would then transparently call. This method will call the generic
`sdhci_probe` which will, during its execution flow, set this bit to 1.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reported-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Adjust the DRAM timing settings for this board per ones provided
by hardware department. The change is applied to the LPDDR4 MR11
register CA ODT configuration, from RZQ/6 to RZQ/3, which fixes
stability issues on subset of boards. The DDR PHY PIE block has
been updated accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Enable GPIO hog support in SPL to match the GPIO hog support in U-Boot proper.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
- integrate bootcount using SNVS_LP general purpose register LPGPR0
- enable link-time optimisation
- explicitly set a boot delay of one second
- enable CRC32 and MD5
- enable command for low-level access to data in a partition
- enable time commands
- enable PMIC commands
- improve ETHPRIME configuration
- enable eMMC HS400 functionality
- enable fixed PHY and MDIO driver model
- remove stale PFUZE100 PMIC driver
- enable thermal management unit driver
- enable more USB host functionality
- enable hexdump
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
"alloc space exhausted" happens in very early stage, which could be seen
with DEBUG_UART options enabled and leeds to an non-functional board.
kontron_pitx_imx8m:
CONFIG_DEBUG_UART_BASE=0x30880000 # for serial3
CONFIG_DEBUG_UART_CLOCK=24000000
imx8mqevk:
CONFIG_DEBUG_UART_BASE=0x30860000 # for uart1
CONFIG_DEBUG_UART_CLOCK=24000000
It is because CONFIG_SYS_MALLOC_F_LEN is too small and still leave
CONFIG_SPL_SYS_MALLOC_F_LEN as 0x2000.
Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
only waiting for TXEMPTY leads to corrupted messages going over the
wire - which is fixed by making use of the FIFO
this change is following the linux kernel uart driver
(drivers/tty/serial/imx.c), which also checks UTS_TXFULL
instead of UTS_TXEMPTY
Signed-off-by: Johannes Schneider <johannes.schneider@leica-geosystems.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
on imx8(mm) the RXDMUXSEL needs to be set for data going over the wire
(as observable on a connected 'scope) to actually make it into the
RXFIFO
the reference manual is not overly clear about this, and only
mentiones that "UCR3_RXDMUXSEL should always be set." - and since the
CR3 register reverts to its reset values after setting the baudrate,
setting this bit is done during '_mxc_serial_setbgr'
Signed-off-by: Johannes Schneider <johannes.schneider@leica-geosystems.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Currently, when running ./scripts/get_maintainer.pl on serial_mxc.c
no i.MX maintainer is returned.
Fix it by adding an entry for this driver.
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
This code part is broken, remove it.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
This code part is broken, remove it.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
- Annotate boot devices available in spl_board_boot_device().
- Drop SD3_BOOT/MMC3_BOOT not available for boot on Verdin iMX8M Mini.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Prepare for optional job ring driver model. Sec may be initialized based
on the job ring information processed from the device tree.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Update the distro config env memory layout for the Verdin iMX8M Mini and
Verdin iMX8M Plus:
- loadaddr=0x48280000 allows for 128.5MB area for uncompressing (ie FIT
images, kernel_comp_addr_r, kernel_comp_size)
- fdt_addr_r = loadaddr + 127.5MB : allows for 127.5MB kernel
- scriptaddr = fdt_addr_r + 512KB : allows for 512KB fdt
- ramdisk_addr_r = scriptaddr + 512KB : allows for 512KB script
Memory layout taken from commit fd5c7173ad
("imx8m{m,n}_venice: update env memory layout") but moved loadaddr by an
additional 0.5MB to avoid "Moving Image from 0x48200000 to 0x48280000"
during booti plus actually defining kernel_comp_size to make booti work.
Note that for our regular BSP Layers and Reference Images for Yocto
Project an updated distro boot script is required (see
meta-toradex-bsp-common/recipes-bsp/u-boot/u-boot-distro-boot).
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Commit 99c7cc58e1 ("ddr: imx: Add i.MX9 DDR controller driver")
contains an inobvious side-effect which renders all systems using
DRAM controller at 3732 MT/s unbootable. The change is located in
ddrphy_init_set_dfi_clk(), where the switch case statement entry
3732 changed to entry 3733, so any board with DDR calibration data
for 3732 MT/s operations needs to be updated to 3733 MT/s to match
the change.
Since there is currently only one such board, update the board instead
of handling both 3732 and 3733 options in the driver. It is likely the
NXP MX8MP RPA update will follow and use the later value too.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The ddrphy_utils.c is now deduplicated in drivers/ddr/imx/phy/ddrphy_utils.c ,
this drivers/ddr/imx/imx8m/ddrphy_utils.c is a remnant from when the
deduplication was implemented and was not removed. Remove it as it is
unused.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Erase the entire U-Boot area during U-Boot update instead of just
a subset of it. This way, in case u-boot-with-spl.imx grows, the
sf write won't write over non-erased part of the SPI NOR.
Signed-off-by: Marek Vasut <marex@denx.de>
Fix copy-paste error of the I2C5 bus recovery GPIO assignment,
the I2C5 GPIOs are on gpio3 instead of gpio5.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Rename imx8mp-dhcom-pdk2-u-boot.dtsi to imx8mp-dhcom-u-boot.dtsi, since
this file is shared by PDK2, PicoITX and DRC02. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
This PHY is not used on PDK2, the header was added due to copy-paste
error, drop it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Add information about which exact SoM variant is used on which PDK2 variant.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Enable both USB CDC ethernet and USB host ethernet on i.MX8M Plus DHCOM.
This is useful for bringing up systems without ethernet plug, but with
either USB host or gadget plug.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: uboot-imx <uboot-imx@nxp.com>
The GW73xx-C revision and onward replaced the 5-port PCIe switch with a
4-port (dropping PCIe to one of the miniPCIe sockets) due to part
availability. This moved the PCI bus of the GbE eth1 device. Use a fixup
to adjust the dt accordingly so that local-mac-address assigned from dt
works on new revision boards.
While we are at it, rename 'blob' to 'fdt' for clarity.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
When the imx8mm.dtsi file was pulled in from Linux, the UARTs
were moved into an spba sub-node which wasn't being included
in the SPL device tree. This meant the references to the UART
weren't being handled properly and when booting the system would
constantly reboot. Fix this by adding the spba node to the spl
device tree to restore normal booting.
Fixes: 4e5114daf9 ("imx8mn: synchronise device tree with linux")
Signed-off-by: Adam Ford <aford173@gmail.com>
wrong end address passed to flush_dcache_range.
modified the flush_dache logic for scatter list elements.
Fixes: 1919f58a8f (crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Fix spurious ampersand in address print e.g.
Find img info 0x&480331a0, size 855
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>"
