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serial: mxc: enable the RX pipeline

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on imx8(mm) the RXDMUXSEL needs to be set for data going over the wire
(as observable on a connected 'scope) to actually make it into the
RXFIFO

the reference manual is not overly clear about this, and only
mentiones that "UCR3_RXDMUXSEL should always be set." - and since the
CR3 register reverts to its reset values after setting the baudrate,
setting this bit is done during '_mxc_serial_setbgr'

Signed-off-by: Johannes Schneider <johannes.schneider@leica-geosystems.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Johannes Schneider 2022-09-06 14:15:03 +02:00 committed by Stefano Babic
parent b7d29fd8a7
commit 25b7ce3287
1 changed files with 13 additions and 0 deletions
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13
drivers/serial/serial_mxc.c
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@ -61,6 +61,11 @@
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
/* imx8 names these bitsfields instead: */
#define UCR3_DTRDEN BIT(3) /* bit not used in this chip */
#define UCR3_RXDMUXSEL BIT(2) /* RXD muxed input selected; 'should always be set' */
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
#define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
@ -176,6 +181,14 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
&base->cr2);
/*
* setting the baudrate triggers a reset, returning cr3 to its
* reset value but UCR3_RXDMUXSEL "should always be set."
* according to the imx8 reference-manual
*/
writel(readl(&base->cr3) | UCR3_RXDMUXSEL, &base->cr3);
writel(UCR1_UARTEN, &base->cr1);
}