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crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish

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HW accelerated hash operations are giving incorrect hash output.
so add flush and invalidate for input/output hash buffers.

Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
This commit is contained in:
Gaurav Jain 2022-05-11 14:23:19 +05:30 committed by Stefano Babic
parent cad77280c3
commit 1919f58a8f
1 changed files with 8 additions and 0 deletions
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8
drivers/crypto/fsl/fsl_hash.c
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@ -149,12 +149,20 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf,
driver_hash[caam_algo].digestsize,
1);
flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len);
flush_dcache_range((ulong)ctx->sha_desc,
(ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
flush_dcache_range((ulong)ctx->hash,
(ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
ret = run_descriptor_jr(ctx->sha_desc);
if (ret) {
debug("Error %x\n", ret);
return ret;
} else {
invalidate_dcache_range((ulong)ctx->hash,
(ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
}
free(ctx);