Commit graph

23 commits

Author SHA1 Message Date
Khoronzhuk, Ivan
f324f2c00b ARM: keystone2: keysonte_nav: add support for K2L SoC
The Keystone2 Lamar SoC uses the same keystone navigator.
Move queue numbers to common hardware file, as all Keystone2 SoCs
have the same ones.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-11-05 13:09:42 -05:00
Vitaly Andrianov
89f44bb0ce keystone2: ecc: add ddr3 error detection and correction support
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.

By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.

An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Vitaly Andrianov
079da2d514 ARM: keystone: msmc: extend functionality of SES
Add functions to set/get SES PMAX values of Pivilege ID pair.
Also add msmc module definitions.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Hao Zhang
95f74dad91 soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Khoronzhuk, Ivan
0935cac685 net: keystone_net: move header file from arch to ti-common
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
b66604fb66 keystone2: enable OSR clock domain for K2L SoC
This patches enables the On-chip Shared Ram clock domain for K2L SoC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
bc45d5729f keystone2: msmc: add MSMC cache coherency support for K2L SOC
This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
c4995a8282 ARM: keystone2: add K2L device hardware definitions
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
WingMan Kwok
bc0e8d7c5d keystone: usb: add support of usb xhci
Add support of usb xhci. xHCI controls all USB speeds of the Host
mode, that is, the SS through the SS PHY, as well as the HS, FS, and
LS through the USB2 PHY. xHCI replaces and supersedes all previous
host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not
backwards compatible with any of them. The USB3SS’s USB Controller is
fully compliant with xHC.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Khoronzhuk, Ivan
afa479cf66 keystone2: keystone_nav: don't use hard addresses in qm_config
Use definitions in qm_config. The definitions can be set specifically
for SoC, so there is no reason to check SoC type while initialization.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Murali Karicheri
6c343825dd ARM: keystone: ddr3: workaround for ddr3a/3b memory issue
This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Keegan Garcia <kgarcia@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-17 21:06:56 -04:00
Vitaly Andrianov
61f66fd5a8 keystone2: use EFUSE_BOOTROM information to configure PLLs
This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-25 10:48:12 -04:00
Hao Zhang
a906847966 board: k2e-evm: add board support
This patch adds Keystone2 k2e_evm evaluation board support.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
20187fd11c ARM: keystone2: add MSMC cache coherency support for K2E SOC
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
5c76f78858 ARM: keystone2: add K2E SoC hardware definitions
This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
3d31538625 k2hk: use common KS2_ prefix for all hardware definitions
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
7b26c1f608 keystone2: add possibility to turn off all dsps
By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
101eec50f0 keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
0b86858956 keystone: ddr3: add ddr3.h to hold ddr3 API
It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
04b7ce0773 ARM: keystone2: psc: use common PSC base
Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
909ea9aa26 ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.c
Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-06-19 17:53:58 -04:00
Murali Karicheri
afee59cd49 keystone: init: enable UART1 to be able use it from kernel
Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.

Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-06-06 17:46:14 -04:00
Vitaly Andrianov
ef509b9063 k2hk: add support for k2hk SOC and EVM
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler
SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please
refer the ti/k2hk_evm/README for details on the board, build and other
information.

This patch add support for keystone architecture and k2hk evm.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
2014-04-17 17:24:38 -04:00