So far we used inline assembly to inject the actual instruction that
triggers the semihosting service. While this sounds elegant, as it's
really only about one instruction, it has some serious downsides:
- We need some barriers in place to force the compiler to issue writes
to a data structure before issuing the trap instruction.
- We need to convince the compiler to actually fill the structures that
we use pointers to.
- We need a memory clobber to avoid the compiler caching the data in
those structures, when semihosting writes data back.
- We need register arguments to make sure the function ID and the
pointer land in the right registers.
This is all doable, but fragile and somewhat cumbersome. Since we now
have a separate function in an extra file anyway, we can do away with
all the magic and just write that in an actual assembly file.
This is much more readable and robust.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
AM62A7-SK board has 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B part
but only 2GB was enabled early.
Enable full 4GB memory by updating the latter 2GB memory region
which gets mapped to 0x0880000000 i.e. DDR16SS0_SDRAM as referred in
Table 2-1. AM62A Common SoC Memory of AM62Ax TRM [1].
[1] : https://www.ti.com/lit/zip/spruj16
Logs: https://gist.github.com/devarsht/e85b6af89c01ddadb3a62f3e5f196af8
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Synchronize devicetree sources with Linux v6.2.
- Use GIC interrupt definitions
- Add reg properties in USB-glue and SoC-glue node
- Fix node names to follow the generic names list in DT specification
- Add L2 cache and AHCI nodes
- Update nand and pcie nodes
- And some trivial fixes
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
UniPhier DT applies its own USB node for U-Boot due to the USB driver
constrains. After solving this issue, u-boot allows the original USB node.
After switching USB node, synchronization of USB node with Linux becomes
possible.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
As the lastest spear directories are removed, delete the associated entry
in Makefile.
Fixes: 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
count_required_pts()'s complexity is high if mappings are not using the
largest possible block size (due to some other requirement such as tracking
dirty pages, for example).
Let's switch to a method that follows the pattern established with
the add_map() helper, and make it almost instantaneous instead of
taking a large amount of time if 2MB mappings are in use instead of
1GB.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 5d756d147e
Link: 6be9330601
In the add_map() function, for each level it populates, it iterates from
the root of the PT tree, making it ineficient if a mapping needs to occur
past level 1.
Instead, replace it with a recursive (and much simpler) algorithm
that keeps the complexity as low as possible. With this, mapping
512GB at level 2 goes from several seconds down to not measurable
on an A55 machine.
We keep the block mappings at level 1 for now though.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the
upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: 96ad729cf4
Link: 6be9330601
Memory used to hold the page tables is allocated from the top of RAM
with no prior initialization and could therefore hold invalid data. As
invalidate_dcache_all() will be called before the MMU has been
initialized and as that function relies indirectly on the page tables
when using CMO_BY_VA_ONLY, these must be in a valid state from their
allocation.
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased
to the upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: e3ceef4230
Exposing set/way cache maintenance to a virtual machine is unsafe, not
least because the instructions are not permission-checked but also
because they are not broadcast between CPUs. Consequently, KVM traps and
emulates such maintenance in the host kernel using by-VA operations and
looping over the stage-2 page-tables. However, when running under
protected KVM, these instructions are not able to be emulated and will
instead result in an exception being delivered to the guest.
Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select
this option and perform by-VA cache maintenance instead of using the
set/way instructions.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Will Deacon <willdeacon@google.com>
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
[ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some
checkpatch warnings. Rebased to upstream. ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: db5507f47f
Link: 2baf54e743
This is used by ls1021atwr_sdcard_ifc_SECURE_BOOT with split config, but
is not needed anymore, since Ethernet migration is complete. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
We don't need to provide an empty arch_misc_init function here, we can
just not enable the hook.
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
If this hooks is needed later, it should be added and populated for
real.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
In this platform, arch_misc_init doesn't perform any real function. The
call to get_soc_type_rev has no lasting side effects.
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
We don't need an empty function, we can just not enable the hook we
don't use.
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
On the lion and evb-px5 platforms, we need this function, so select it.
Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Cc: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
The function arch_early_init_r only does anything on these platforms if
we have FPGA (or SPL and SPL_FPGA) enabled, so move the logic to select
based on that.
Cc: Michal Simek <michal.simek@amd.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We need to be calling arch_early_init_r() on 64bit mvebu platforms, so
move this to a select.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
In SPL are active memory maps set by the BootROM. Define them in cpu.h file
to the correct values. Some peripherals are not mapped at all.
Signed-off-by: Pali Rohár <pali@kernel.org>
Proper U-Boot moves SPI0 CS0 Flash mapping from 0xD4000000 to 0xF4000000
and change its size from 64 MB to 8 MB. Definitions are already in
MBUS_SPI_BASE/MBUS_SPI_SIZE macros. So define these macros also for SPL
build, use them in env_sf_get_env_addr() function and move this function
from spl.c to cpu.c to be available in Proper U-Boot too.
Signed-off-by: Pali Rohár <pali@kernel.org>
MVEBU_SPL_BOOT_DEVICE_SPI is for NOR flash. Either serial or parallel. Not
for general serial/SPI devices. The correct name should be BOOT_DEVICE_NOR
but name SPI is already used in mkimage config format which we do not want
to change for compatibility reasons.
MVEBU_SPL_BOOT_DEVICE_MMC is for MMC and SD compatible devices. Not for
SDIO devices. In most cases used for eMMC or SD card.
Signed-off-by: Pali Rohár <pali@kernel.org>
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_PEX which instruct
make to generate kwbimage with PEX header. This image is used for booting
from PCI Express device which is in the Root Complex mode.
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then start
executing U-Boot proper.
Signed-off-by: Pali Rohár <pali@kernel.org>
Add a new Kconfig option CONFIG_MVEBU_SPL_BOOT_DEVICE_NAND which instruct
make to generate kwbimage with NAND header. This image is used for booting
from NAND flash (either SPI or parallel).
Support is very simple, SPL after finishes DDR training returns back to the
BootROM (via CONFIG_SPL_BOOTROM_SUPPORT option) and BootROM then loads and
executes U-Boot proper.
To generate correct kwbimage NAND header, it is required to set following
Kconfig options:
CONFIG_SYS_NAND_PAGE_SIZE
CONFIG_SYS_NAND_BLOCK_SIZE
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION
They are used only by make / mkimage when generating final kwbimage.
CONFIG_MVEBU_SPL_NAND_BADBLK_LOCATION is a new mvebu specific Kconfig
option which is set into kwbimage NAND_BADBLK_LOCATION header field.
Signed-off-by: Pali Rohár <pali@kernel.org>
Marvell BootROM loads MMC image from sector 0 (HW boot or data partition)
and SD image from sector 1.
So for SD card booting it is needed to not use constant CONFIG MMC options
and instead of them it is needed to define functions spl_mmc_boot_mode()
spl_mmc_get_uboot_raw_sector() which determinate offsets at SPL runtime
based on MMC or SD card.
Calculation of SD card sector expects following values:
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
When eMMC boot is selected then BootROM loads kwbimage header (U-Boot SPL)
from the selected eMMC boot partition. So for eMMC boot ensure that U-Boot
SPL loads U-Boot proper (from kwbimage) also from the same selected eMMC
boot partition.
Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2 are representing mmc dev 1 but all
Armada SoCs have only one mmc controller. So remove references to
non-existent second mmc controller.
Fixes: f830703f42 ("arm: mvebu: Check that kwbimage blockid matches boot mode")
Signed-off-by: Pali Rohár <pali@kernel.org>
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.
To process SATA kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr as relative offset to
the main header. This change fixes booting of U-Boot proper from SPL code
in SATA image.
Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).
To process SDIO kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr in bytes. This change
fixes booting of U-Boot proper from SPL code stored in SDIO image.
Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypt BCT.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypted BCT.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.
Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This function allows to convert a device tree clock ID to PLL ID.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This mappings were missing for some reason.
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This file is included by the different chameleonv3 variants. Change the
name to .dtsi.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
i2c updates for v2023.04
- add new i2c driver ast2600 from Ryan Chen
- i2c-cdns: make read fifo-depth configurable through device tree
from Pei Yue Ho
- mxc i2c driver: print base address in hex, not in decimal
from Fabio
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is
required for this board to boot over UART with kwboot. Enable this in
kirkwood-pogoplug-series-4-u-boot.dtsi.
Added by Stefan while applying:
Please note that it's not fully understood, why this property really
is needed. Here a link to the discussion about this:
https://lore.kernel.org/r/20230201080210.ypz4nrj4y2igwxz3@pali/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
