Commit graph

4374 commits

Author SHA1 Message Date
Jim Liu
0ae1c77199 misc: nuvoton: Add NPCM7xx otp controller driver
Add Nuvoton BMC npcm750 otp driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Jim Liu
9e03b48dfa crypto: nuvoton: Add NPCM7xx AES driver
add nuvoton BMC npcm750 AES driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-06-22 21:30:05 -04:00
Chia-Wei Wang
12770d0df0 ast2600: spl: Add boot mode detection
AST2600 supports boot from SPI(mmap), eMMC, and UART.
This patch adds the boot mode detection and return the
corresponding boot device type.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2022-06-22 21:30:05 -04:00
Tom Rini
52af0101be Merge branch 'master' into next
Merge in v2022.07-rc5.
2022-06-20 14:40:59 -04:00
Michael Walle
2a9cf320af armv8: layerscape: add missing RCW source defines
A board might need to get the source of the RCW word, which is also the
boot source in most cases.

These defines are taken from the LS1028A and I expect they are the same
across the SoCs with the same chassis, after all, there was already a
reset source for NOR flash.

Signed-off-by: Michael Walle <michael@walle.cc>
2022-06-20 15:52:45 +08:00
Andre Przywara
ce9c579e2b armv8: always use current exception level for TCR_ELx access
Currently get_tcr() takes an "el" parameter, to select the proper
version of the TCR_ELx system register.
This is problematic in case of the Apple M1, since it runs with
HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout,
and we get the wrong version.

For U-Boot's purposes the only sensible choice here is the current
exception level, and indeed most callers treat it like that, so let's
remove that parameter and read the current EL inside the function.
This allows us to check for the E2H bit, and pretend it's EL1 in this
case.

There are two callers which don't care about the EL, and they pass 0,
which looks wrong, but is irrelevant in these two cases, since we don't
use the return value there. So the change cannot affect those two.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2022-06-16 15:22:55 -04:00
Tom Rini
3135ba642f arm: pxa: Remove CONFIG_CPU_PXA25X
There are no platforms that set this, remove the code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
6074a536d5 ppc / layerscape: Clean up CONFIG_SYS_CCSR_DO_NOT_RELOCATE usage
A number of PowerPC platforms define this, for SPL.  To move this to
Kconfig, it needs to be CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE, so use
CONFIG_IS_ENABLED() to check for usage.  A number of layerscape
platforms bring this logic from PowerPC, but only need a small part of
it, for the fman driver.  Remove their unused portion at least.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Tom Rini
12f613cf0e arm: omap2plus: Move CONFIG_SYS_PTV out of CONFIG namespace
This is always defined to 2, and referenced in two places.  Move the
define to <asm/omap_common.h> and make sure the code that uses this
includes that file.  Make <asm/arch-omap*/clock.h> not include that
file, as we don't need to be doing so.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:00 -04:00
Andre Przywara
2b641211c5 armv8: Fix TCR 64-bit writes
The AArch64 TCR_ELx register is a 64-bit register, and many newer
architecture features use bits in the upper half. So far U-Boot was
igorant of those bits, trying to leave them alone.
However, in an effort to set bit 31 to 1, it failed doing so, because
the compiler sign-extended "1 << 31", so that all bits[63:31] got set.

Older ARMv8.0 cores don't define anything dangerous up there, but newer
architecture revisions do, and setting all those bits will end badly:
=================
$ qemu-system-aarch64 -cpu max ....
U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100)

DRAM:  1.5 GiB
=================  (hangs here)

Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all
upper bits stay at a safe 0 value. This means no more surprises when
U-Boot runs on a more capable CPU core.

Reported-by: Balaji Anandapadmanaban <Balaji.Anandapadmanaban@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Peter Collingbourne <pcc@google.com>
2022-06-03 11:15:24 -04:00
Gaurav Jain
cad77280c3 i.MX8ULP: add display_ele_fw_version api
implement get f/w version api.
print ele f/w version in spl.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
2022-05-20 12:36:47 +02:00
Rasmus Villemoes
290ffe5788 imx8m: fix reading of DDR4 MR registers
I was trying to employ lpddr4_mr_read() to something similar to what
the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM
type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c
differs from the private one used by that board in how it extracts the
byte value, and I was only getting zeroes. Adding a bit of debug
printf'ing gives me

 tmp = 0x00ffff00
 tmp = 0x00070700
 tmp = 0x00000000
 tmp = 0x00101000

and indeed I was expecting a (combined) value of 0xff070010 (0xff
being Manufacturer ID for Micron). I can't find any documentation that
says how the values are supposed to be read, but clearly the iot-gate
definition is the right one, both for its use case as well as my
imx8mp-based board.

So lift the private definition of lpddr4_mr_read() from the
imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration
in the ddr.h header where e.g. get_trained_CDD() is already declared.

This has only been compile-tested for the imx8mm-cl-iot-gate
board (since I don't have the hardware), but since I've merely moved
its definition of lpddr4_mr_read(), I'd be surprised if it changed
anything for that board.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00
Marek Vasut
c329f9349b ARM: imx: imx31: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
be23774ed1 ARM: imx: imx27: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Marek Vasut
52b6b480db ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)
Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base
address. Convert all board configurations to this new macro. This is the
first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a
clean up, no functional change.

The new macro contains compile-time test to verify N is in suitable
range. The test works such that it multiplies constant N by constant
double-negation of size of a non-empty structure, i.e. it multiplies
constant N by constant 1 in each successful compilation case.

The non-empty structure may contain C11 _Static_assert(), make use of
this and place the kernel variant of static assert in there, so that
it performs the compile-time check for N in the correct range. Note
that it is not possible to directly use static_assert in compound
statements, hence this convoluted construct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-05-20 09:03:01 +02:00
Jim Liu
84335544ea arm: nuvoton: Add support for Nuvoton NPCM750 BMC
Add basic support for the Nuvoton NPCM750 EVB (Poleg).

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-05-05 09:28:47 -04:00
Tim Harvey
e3bdc97148 pci: imx: remove weak overrides no longer used
There are no users of the imx6_pcie_toggle_power and imx6_pcie_toggle_reset
weak overrides and as these functions are able to be handled now via dt
properties lets remove these.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-04-21 14:38:03 +02:00
Tim Harvey
6f6e069ca3 pci: imx: use vpcie-supply if defined by device-tree
If vpcie-supply is defined by device-tree use that if
CONFIG_PCIE_IMX_POWER_GPIO is not defined.

Note that after this the following boards which define
CONFIG_PCIE_IMX_POWER_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
 - mx6sabresd
 - mx6sxsabresd
 - novena

Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_POWER_GPIO and does
not have vpcie-supply defined in it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_POWER_GPIO globally can't be done until that board adds
vpcie-supply.

Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-04-21 14:38:03 +02:00
Marek Vasut
19842b6a20 imx: power-domain: Inline arch-imx8m/power-domain.h
The arch/arm/include/asm/arch-imx8m/power-domain.h is not included
anywhere except in drivers/power/domain/imx8m-power-domain.c, just
inline the content and drop the header. No functional change.

Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-04-21 12:44:23 +02:00
Johan Jonker
33f4750783 rockchip: rk3066: add core support
Add the core architecture code for the rk3066.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Paweł Jarosz
730a402450 rockchip: rk3066: add clock driver for rk3066 soc
Add the clock driver for the rk3066 platform.

Derived from the rk3288 and rk3188 driver it
supports only a bare minimum to bring up the system
to reduce the TPL size for:
  SDRAM clock configuration.
  The boot devices NAND, EMMC, SDMMC, SPI.
  A UART for the debug messages (fixed) at 115200n8.
  A SARADC for the recovery button.
  A TIMER for the delays (fixed).

There's support for two possible frequencies,
the safe 600MHz which will work with default pmic settings and
will be set to get away from the 24MHz default and
the maximum of 1.416Ghz, which boards can set if they
were able to get pmic support for it.

After the clock tree is set during the TPL probe
there's no parent update support.

In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c
obtain the (fixed) clk_get_rate from the clock driver
instead of platdata.

The rk3066 cru node has a number of assigned-clocks properties
that call the .set_rate() function. Add them to the list so that
they return a 0 instead of -ENOENT.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Paweł Jarosz
e6b0ed0e74 rockchip: rk3066: add grf header file
grf is needed by various drivers for rk3066 soc.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18 11:25:13 +08:00
Jesse Taube
a2d6fbf5ff clk: imxrt: Use dts for anatop base address
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-04-12 21:08:23 +02:00
Michael Trimarchi
1dd4985ed4 imx8m: add init_nand_clk
Add init_nand_clk to enable gpmi nand clock. Since i.MX8M not use CCF,
so we still use legacy mode to configure the clock.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-04-12 19:10:44 +02:00
Michael Trimarchi
1247c444d6 imx8m: add regs used by GPMI
Add regs used by GPMI

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-04-12 19:10:44 +02:00
Peng Fan
fd437083b8 imx: imx8mp: Add iMX8MP UltraLite Part cpu type
Add i.MX8MP UltraLite Part CPU type

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 19:10:43 +02:00
Peng Fan
f342c9e381 imx: dynamic setting mmcdev and mmcroot
Dynamic setting mmcdev and mmcroot.
Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 19:10:43 +02:00
Ye Li
203412f66d misc: S400_API: Update S400 API for buffer dump
Add ahab_dump_buffer API to dump AHAB buffer for debug purpose

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:57 +02:00
Clement Faure
a55ca506c9 misc: S400_API: add ahab_release_caam
Add ahab_release_caam() function to the S400 API.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:56 +02:00
Ye Li
4ab38f6822 imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:56 +02:00
Peng Fan
a092f33305 imx: imx8ulp: add ND/LD clock
Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.

Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:56 +02:00
Peng Fan
40d60ec780 imx: imx8ulp: add CAAM clock entry
Add CAAM clock entry in PCC3

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:56 +02:00
Ye Li
5579d66e37 imx: imx8ulp: Add M33 handshake functions
Add functions to check if M33 image is booted and handshake with M33
image via MU. A core notifies M33 to start init by FCR F0, then wait
M33 init done signal by checking FSR F0.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:56 +02:00
Peng Fan
8576f1a67a imx: imx8ulp: include pcc/cgc header in clock header
With this change, we no need to include pcc/cgc header files both.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12 17:33:56 +02:00
Tommaso Merciai
625a3fe90c arch: mach-imx: imx8m: add pwm_regs struct in imx-regs
Add pwm_regs struct for i.MX8MM SOC

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-12 17:33:55 +02:00
Tommaso Merciai
4aee7d0b84 arch: mach-imx: imx8m: add pwm ctrl registers fields defines
Add pwm control registers fields defines into imx-regs.h:

 - prescaler
 - dozeen
 - waiten
 - dbgen
 - clksrc_ipg_high
 - clksrc_ipg, en field

References:
 - iMX8MMRM.pdf p 3884

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
2022-04-12 17:33:55 +02:00
Marek Vasut
e26d0152d6 ARM: imx: Decode ECSPI env location from i.MX8M ROMAPI tables
Decode ECSPI boot device in env_get_location() from i.MX8M ROMAPI tables.
This is necessary to correctly identify env is in SPI NOR when the system
boots from SPI NOR attached to ECSPI.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-12 17:33:55 +02:00
Gaurav Jain
cb5d0419f5 crypto/fsl: i.MX8: Enable Job ring driver model.
i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
2022-04-12 11:19:21 +02:00
Tom Rini
2fc0995cc0 arm: Remove unused ep93xx code
There are no platforms for this architecture anymore, remove unused
code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08 10:46:22 -04:00
Tom Rini
4de720e98d Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-05 08:33:32 -04:00
Jernej Skrabec
1772771ac0 sunxi: prcm: Add a few registers
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Angelo Dureghello
482c1ccd1c sunxi: H3: fix non working console on uart2
Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.

Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
44de13d945 sunxi: Support SPL in both eGON and TOC0 images
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
458e59da5d pwm: sunxi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:17 +01:00
Samuel Holland
aadf3d5383 sunxi: Remove options and setup code for I2C2-I2C4
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
3e42d919af sunxi: Remove non-DM GMAC pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
12bd00aafc net: sunxi_emac: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:24:16 +01:00
Samuel Holland
b799eabc7e sunxi: pinctrl: Create the driver skeleton
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04 23:23:50 +01:00
Sean Anderson
6d16157426 arm64: Import some ESR and SPSR defines from Linux
This imports some defines for esr and spsr from Linux v5.16. I have
modified the includes and fixed some indentation nits but otherwise it
is the same. There are a lot more defines than we need, but it doesn't
hurt.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00
Sean Anderson
e75d791c50 arm64: Save spsr in pt_regs
This register holds "pstate" which includes (among other things) the
instruction mode the CPU was in when the exception was taken. This is
necessary to correctly interpret instructions at elr.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-01 16:56:53 -04:00