Commit graph

42 commits

Author SHA1 Message Date
Amit Kumar Mahapatra
a13e0821da ARM: zynq: Fix size-cells for pl353 driver
"size-cells" of the nand controller node should be 0 as the "reg"
property of the nand device node contains the chip select number and not
address information.
The patch fixes the below compilation warning
arch/arm/dts/zynq-zc770-xm011.dtb: Warning (reg_format):
/axi/memory-controller@e000e000/nand-controller@0,0/nand@0:reg: property
has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6e90665a2dad7fe8ade10b8f57101f8144963791.1655288559.git.michal.simek@amd.com
2022-06-24 14:18:02 +02:00
Michael Walle
03a8e826e0 ARM: dts: zynq: add NAND flash controller node
Recently, a driver for the ARM Primecell PL35x static memory controller
(including NAND controller) was added in linux. Add the corresponding
device tree node.

Also update cfi-flash registers and location in DT.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210616155437.27378-3-michael@walle.cc
Link: https://lore.kernel.org/r/ee81d3846a1ce93f240d61537d404796e5599c1c.1645625433.git.michal.simek@xilinx.com
2022-03-07 08:52:20 +01:00
Michal Simek
767aa16d41 ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."

Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml

Similar change has been done for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
2021-06-23 09:48:35 +02:00
Zumeng Chen
d12c8ccdc4 ARM: dts: zynq: enablement of coresight topology
This patch is to build the coresight topology structure of zynq-7000
series according to the docs of coresight and userguide of zynq-7000.

Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14 09:05:56 +01:00
Michal Simek
233750d3a1 ARM: zynq: Add missing pl353-smc node
DT binding was reviewed in Linux by commit b0b41af12a1b
("dt-bindings: memory: Add pl353 smc controller devicetree binding
information") that's why this fragment can be also added to U-Boot
repository.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
7b85f7901d ARM: dts: Use mmc@ instead sdhci@
mmc name is recommended based on devicetree specification.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-15 15:04:00 +01:00
Michal Simek
e7f327fe4d arm: zynq: Add efuse node for Zynq-7000S devices
Add access to efuse for Zynq-7000S device detection.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 14:58:45 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Michal Simek
427d568c31 arm: zynq: Fix pmu register description coding style
Drop the space before/after '<' and '>'; and
separate the entries to be a bit more readable.

Reported-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-01-30 14:28:54 +01:00
Michal Simek
534f7e0235 arm: zynq: Sync location of DT properties with Linux
This is trival change which only ensures the same location with Linux
kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 15:53:08 +01:00
Michal Simek
0b180d02a3 arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
2017-08-02 09:11:51 +02:00
Stefan Herbrechtsmeier
781745bd87 zynq: Move zynq to clock framework
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Michal Simek
5af46ca71a ARM: zynq: Remove spi-max-frequency
spi-max-frequency for spi bus depends on devices which are
connected to it. Remove this parameter from dtsi file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-01-10 10:18:11 +01:00
Moritz Fischer
720ba46e71 ARM: dt: zynq: Add labels to cpu nodes to allow overriding OPPs.
By adding labels to the cpu nodes in the dtsi, a dts that
includes it can change the OPPs by referencing the cpu0
through the label.

[Based on linux (400b6a0cbef55d1ae32808eaa1ef1c28820bf6ac)]
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: u-boot@lists.denx.de
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-12-20 09:15:27 +01:00
Michal Simek
cc7978bef9 ARM: zynq: Remove DTC 1.4.2 warnings
DTC 1.4.2 reports these warnings:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property,
but no unit name
Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name,
but no reg property

This patch is fixing them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15 15:30:38 +01:00
Masahiro Yamada
621a93e140 ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus
Commit 9f56917ab8 ("dm: core: make simple-bus compatible to
simple-mfd") made possible to import the following commit:

Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1

The SLCR (System-Level Control Registers) block is an MFD (Multi
Function Device) rather than a bus.

"simple-mfd" seems a more suitable compatible string than "simple-bus".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24 11:15:00 +02:00
Michal Simek
77bb73decb ARM: zynq: Align devcfg node
- Have compatible string as the first property
- Sync with Linux kernel dtsi
- Add missing interrupt properties

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:01 +02:00
Moritz Fischer
20fe3f1791 ARM: dts: Updated devicetree bindings for Zynq 7000 platform
Added addtional bindings required for FPGA Manager operation
of the Xilinx Zynq Devc configuration interface.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:01 +02:00
Moritz Fischer
4c987271b3 ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:01 +02:00
Michal Simek
58fab4cd9c ARM: zynq: Add interrupt-controller property to gpio nodes
GPIO driver supports an input interrupt that's why gpio node itself can
be labeled as interrupt controller.

Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13 18:29:01 +02:00
Michal Simek
e5c343dddc ARM: zynq: Clean DTSI coding style
Fix minor indentation problems.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-01-27 15:55:55 +01:00
Simon Glass
035c6b271d arm: zynq: dts: Add U-Boot device tree additions
We need to mark some device tree nodes so that they are available before
relocation. This enables driver model to find these automatically. In the
case of SPL it ensures that these nodes will be retained in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-11-04 14:49:53 +01:00
Jagan Teki
70676cb3b5 dts: zynq: Add zynq qspi controller nodes
This patch adds zynq qspi controller nodes in zynq-7000.dtsi.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:01 +05:30
Michal Simek
d50cb3d64b ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree.

Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:26 +02:00
Michal Simek
b4e9eaf71f ARM: zynq: DT: Get rid of ps-clk-frequency
ps-clk-frequency is platform specific setting and shouldn't be the part
of DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:25 +02:00
Michal Simek
05e7ca63b7 ARM: zynq: DT: Update years in copyright
Trivial.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:25 +02:00
Michal Simek
461c388806 ARM: zynq: DT: Add reference to bus node
For adding OCM memory in platform DTS is necessary to have reference to
amba bus.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:24 +02:00
Michal Simek
e913ce2ad5 ARM: zynq: DT: Add pinctrl node
Add pinctrl node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:24 +02:00
Michal Simek
5ee236a3ea ARM: zynq: DT: Cleanup address-cells and size-cells
Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:24 +02:00
Michal Simek
b346bd1d2d ARM: zynq: DT: Clean up timer device tree nodes
Separate IRQ cells from each other for easier reading.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:23 +02:00
Michal Simek
7e163363fb ARM: zynq: DT: Use the zynq binding with macb
Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.

Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:23 +02:00
Michal Simek
08305feb8e ARM: zynq: DT: Fix GEM register area size
The size of the GEM's register area is only 0x1000 bytes.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
40b383fa84 spi: Fix zynq SPI binding
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
3ffcdc7aaf ARM: zynq: DT: Remove 222 MHz OPP
Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
8a8c46a65d ARM: zynq: DT: Migrate UART to Cadence binding
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:22 +02:00
Michal Simek
bece06ce0c ARM: zynq: DT: Add a fixed regulator for CPU voltage
To silence the warning
   cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:21 +02:00
Michal Simek
fb1a5061f0 ARM: zynq: DT: Add missing nodes to DTSI
Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:21 +02:00
Michal Simek
a0cb47f1a1 ARM: zynq: DT: Use the right names for nodes
Based on SPEC you right names with addresses.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28 11:56:21 +02:00
Jagan Teki
cdc9dd0750 spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.

Ex:
&spi1 {
	status = "okay";
};

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Jagan Teki
a8a8fc9cee dts: zynq: Add zynq spi controller nodes
This patch adds zynq spi controller nodes in zynq-7000.dtsi.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Masahiro Yamada
580a54c5d4 zynq: import zynq-7000.dtsi from Linux Kernel
Our current motivation is to use OF initialization for RAM and UART.
But adding full DTS would be helpful in future, for instance,
for OF configuration of Ethernet, MMC, USB, etc.

This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5
and adjusts the license comment block for SPDX.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-15 13:57:29 +02:00
Jagannadha Sutradharudu Teki
f8f36c5dda dts: zynq: Add basic fdt support
This patch provides a basic fdt support for zynq u-boot.

zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.

u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed

Enabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2014-01-10 15:18:33 +01:00