The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.
On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.
On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc. Another 1.2kB of code comes in for
the function __umoddi3.
It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.
Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: York Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We utilize the compatible string to find the node to add fsl,liodn
property to. However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.
Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.
Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix up the device tree property associated with the IEEE 1588 timer
source frequency. Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support). The eTSEC clock is ccb_clk/2.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it. Also we only have one Fman so no need for the code to deal with
a second.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.
We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)
On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL. On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.
On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage
device support using PCI EHCI module.
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Changed the following DDR timing parameters for 800Mt/s:
tRRT BL/2+1 to BL/2
tWWT BL/2+1 to BL/2
tWRT BL/2+1 to BL/2
tRWT BL/2+1 to BL/2
REFINT 6500ns to 7800ns
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
RevB boards never really made it outside of Freescale and have been
replaced with RevC & RevD which had various board bug fixes.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PCA9557 is parallel I/O expansion device on I2C bus which stores various
board switch settings like NOR Flash-Bank selection, SD Data width.
On board:
switch SW5[6] is to select width for eSDHC
ON - 4-bit [Enable eSPI]
OFF - 8-bit [Disable eSPI]
switch SW4[8] is to select NOR Flash Bank for Booting
OFF - Primary Bank
ON - Secondary Bank
Read board switch settings on p1_p2_rdb and configure corresponding
eSDHC width.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash
boot loaders because:
- P1_P2_RDB boards have soldered DDR so no need for SPD
- Also P102x has 256K L2 cache size so becomes a limiting factor for
size of image that could be loaded in SRAM mode and would require three
stage boot loader (TPL).
Changes done:
1. CONFIG_SYS_TEXT_BASE to 0x11000000
2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The NXID EEPROM format comes in two versions, v0 and v1. The only
difference is in the number of MAC addresses that can be stored. NXID v0
supports eight addresses, and NXID v1 supports 23.
Rather than allow a board to choose which version to support, NXID v0 is
now considered deprecated. The EEPROM code is updated to support only
NXID v1, but it can still read EEPROMs formatted with v0. In these cases,
the EEPROM data is loaded and the CRC is verified, but the data is stored
into a v1 data structure. If the EEPROM data is written back, it is
written in v1 format. This allows existing v0-formatted EEPROMs to
continue providing MAC addresses, but any changes to the data will force
an upgrade to the v1 format, while retaining all data.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR
and SDHC erratum.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.
P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.
Added comments in config_mpc85xx.h to denote single core versions of
processors.
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add ULI1575 EHCI controller to the list of the supported devices.
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.
In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register
Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.
To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
(features doesn't exist on P1023/P1017)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can simplify some cpu/SoC level initialization by moving it to be
after the environment and non-volatile storage is setup as there might
be dependancies on such things in various boot configurations.
For example for FSL SoC's with QE if we boot from NAND we need it setup
to extra the ucode image to initialize the QE. If we always do this
after environment & non-volatile storage is working we can have the code
be the same regardless of NOR, NAND, SPI, MMC boot.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move some processor specific QE defines into config_mpc85xx.h and use
QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct.
Also fixed up some comment style issues in immap_qe.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Read MAC address from EEPROM. Add hwconfig settings.
Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.
Also cleanup some of the boot commands.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9
respectively).
We enable EXT2, FAT, and parition support for both MMC & USB configs.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In a manner similar to passing ethernet stashing parameters into device
tree for "gianfar", extend the support to the "fsl,etsec2" as well.
Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC
SOCs. Although programming the ngPIXIS is mostly standard on all boards that
have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in
"indirect" mode whenever the video display (DIU) is active.
To support indirect mode, and to make it easier to support other quirks on
future reference boards, the low-level ngPIXIS functions are all marked as
weak, so that board-specific code can override any of them. We take advantage
of this feature on the P1022DS, so that we can properly reset the board when
the DIU is active.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.
Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
configurable
page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
availble at
boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
e.g. SRAM, ROM
- External clock is supported with programmable division
ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
on I/O bus
- 32 bit I/O: AD
- 16 bit I/O: AADD
- 8 bit I/O : AAAADDDD
- Configurable Even/Odd Parity on Address/Data bus
supported
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Au1x00 is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Thomas Lange <thomas@corelatus.se>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
IncaIP is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
