Commit graph

54408 commits

Author SHA1 Message Date
Álvaro Fernández Rojas
9ab403d0dd bmips: bcm6338: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
ccfd69883a dma: add bcm6348-iudma support
BCM6348 IUDMA controller is present on multiple BMIPS (BCM63xx) SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:00 +01:00
Rick Chen
368ff57805 doc: README.ae350: Sync for ax25-ae350 rename
Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 13:26:02 +08:00
Rick Chen
ab3f92dee6 riscv: configs: Rename ax25-ae350 defconfig
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.

Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 13:25:55 +08:00
Anup Patel
9acaf60bfd riscv: qemu: Imply SIFIVE_SERIAL for emulation
This patch enables SiFive UART driver for QEMU RISC-V emulation
by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Anup Patel
e2842496ac drivers: serial: Add SiFive UART driver
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Bin Meng
dcad9b8d66 riscv: Remove ae350.dts
This is not used by any board. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3c85099aa3 riscv: bootm: Change to use boot_hart from global data
Avoid reading mhartid CSR directly, instead use the one we saved
in the global data structure before.

With this patch, BBL no longer needs to be hacked to provide the
mhartid CSR emulation for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
51ab4570f3 riscv: Save boot hart id to the global data
At present the hart id passed via a0 in the U-Boot entry is saved
to s0 at the beginning but does not preserve later. Save it to the
global data structure so that it can be used later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
7f5d35a547 riscv: Adjust the _exit_trap() position to come before handle_trap()
With this change, we can avoid a forward declaration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
10753ef8fd riscv: Return to previous privilege level after trap handling
At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
496262cca6 riscv: Fix context restore before returning from trap handler
sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
4b3f5ed5ac riscv: Move trap handler codes to mtrap.S
Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
485e822346 riscv: Do some basic architecture level cpu initialization
In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
57fe5c64cb riscv: Add indirect stringification to csr_xxx ops
With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
aef59e5cc4 riscv: Update supports_extension() to use desc from cpu driver
This updates supports_extension() implementation to use the desc
string from the cpu driver whenever possible, which avoids the
reading of misa CSR for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3967156464 riscv: Add exception codes for xcause register
This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
ea53f1c742 riscv: Add CSR numbers
The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3c276b2703 riscv: Remove non-DM version of print_cpuinfo()
With DM CPU driver, the non-DM version of print_cpuinfo() is no
longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
39cad5bc0b riscv: Probe cpus during boot
This calls cpu_probe_all() to probe all available cpus.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
92b64fef05 riscv: Enlarge the default SYS_MALLOC_F_LEN
Increase the heap size for the pre-relocation stage, so that CPU
driver can be loaded.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
84304d4866 riscv: qemu: Add platform-specific Kconfig options
Add the QEMU RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Anup Patel
511107d85d riscv: Implement riscv_get_time() API using rdtime instruction
This adds an implementation of riscv_get_time() API that is using
rdtime instruction.

This is the case for S-mode U-Boot, and is useful for processors
that support rdtime in M-mode too.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18 09:56:27 +08:00
Bin Meng
644a3cd77e riscv: Add a SYSCON driver for SiFive's Core Local Interruptor
This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.

This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Anup Patel
3cfc825261 riscv: Introduce a Kconfig option for machine mode
So far we have a Kconfig option for supervisor mode. This adds an
option for the machine mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-18 09:56:26 +08:00
Bin Meng
44fe795c14 riscv: ax25: Hide the ax25-specific Kconfig option
There is no need to expose RISCV_NDS to the Kconfig menu as it is
an ax25-specific option. Introduce a dedicated Kconfig option for
the cache ops of ax25 platform and use that to guard the cache ops.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-12-18 09:56:26 +08:00
Bin Meng
60262cd041 timer: Add generic driver for RISC-V privileged architecture defined timer
RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32, RV64, and RV128 systems.

Different platform may have different implementation of the mtime
block hence an API riscv_get_time() is required by this driver for
platform codes to hide such implementation details. For example,
on some platforms mtime is provided by the CLINT module, while on
some other platforms a simple 'rdtime' can be used to get the timer
counter.

With this timer driver the U-Boot timer functionalities like delay
works correctly now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Bin Meng
833508c05c cpu: Add a RISC-V CPU driver
This adds a driver for RISC-V CPU. Note the driver will bind
a RISC-V timer driver if "timebase-frequency" property is
present in the device tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Bin Meng
27dc2c130e riscv: qemu: Create a simple-bus driver for the soc node
To enumerate devices on the /soc/ node, create a "simple-bus"
driver to match "riscv-virtio-soc".

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Bin Meng
b859694776 dm: cpu: Add timebase frequency to the platdata
This adds a timebase_freq member to the 'struct cpu_platdata', to
hold the "timebase-frequency" value in the cpu or /cpus node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Lukas Auer
8176ea4d58 riscv: add Kconfig entries for the code model
RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.

By default, medlow is selected for U-Boot on both 32-bit and 64-bit
systems.

The -mcmodel compiler flag is selected according to the Kconfig
configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
[bmeng: adjust to make medlow the default code model for U-Boot]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:26 +08:00
Tom Rini
1f2e948d6d Prepare v2019.01-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-17 20:25:24 -05:00
Sam Protsenko
528920f94e arm: ti: boot: Increase system partition size
Android code base is growing, so since Android "Pie" the size of
system.img grew up to be about 740 MiB. Let's increase system.img to
1 GiB to accommodate for those changes and leave some margin for future
changes. We don't want to make it more than 1 GiB, because we should
keep userdata partition big enough (for user files, like media etc.),
and eMMC size on BeagleBoard-X15 is only 3.5 GiB.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Praneeth Bajjuri <praneeth@ti.com>
2018-12-17 08:42:19 -05:00
Chris Packham
a267699bea Makefile: output migration warnings to stderr
Output the device model migration warnings to stderr. This allows tools
like buildman to pick them up rather than suppressing them along with
the normal build output on stdout.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-12-17 07:15:41 -05:00
Stefano Babic
24431adc36 Restore compatibility of image type IDs
Commit a2b96ece5b breaks the enumeration
of the Image Types. New image types can be appended, but they cannot be
inserted in the list else backward compatibility is broken.

This restores the images types as before 2018.11 and move i.MX8 related
images at the end.

Signed-off-by: Robert Berger <robert.berger@ReliableEmbeddedSystems.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <trini@konsulko.com>
2018-12-17 07:09:29 -05:00
Denis Zalevskiy
4c55208350 board: ge: Move VPD EEPROM configuration to the defconfig
Use standard configuration logic to define EEPROM constants.
Names are based on VPD_EEPROM_ prefix because EEPROM_ is already
used by i2c_eeprom driver.

Signed-off-by: Denis Zalevskiy <denis.zalevskiy@ge.com>
Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.com>
2018-12-17 10:46:04 +01:00
Denis Zalevskiy
33a6c8d4e6 board: ge: Remove EEPROM bus param from read_vpd()
The bus is statically defined, so remove redundant parameters
from read_vpd() for PPD and Bx50v3.

Signed-off-by: Denis Zalevskiy <denis.zalevskiy@ge.com>
Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.com>
2018-12-17 10:46:04 +01:00
Pierre-Jean Texier
7f4269b24a warp7: configs: add CONFIG_FIT option
This enable FIT image support.

Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io>
2018-12-17 10:46:04 +01:00
Tom Rini
d597b26d51 Improvements and fixes or u-boot-rockchip:
- new board: adds rv1108-elgin-r1 board support
 - rk3288-evb: dts: remove 'vmmc' from emmc node
 - rk3399-puma: dts: remove obsolete DTS node 'vcc5v0_host'
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Merge tag 'for-master-20181216' of git://git.denx.de/u-boot-rockchip

Improvements and fixes or u-boot-rockchip:
- new board: adds rv1108-elgin-r1 board support
- rk3288-evb: dts: remove 'vmmc' from emmc node
- rk3399-puma: dts: remove obsolete DTS node 'vcc5v0_host'
2018-12-16 20:49:46 -05:00
Otavio Salvador
e11ef3d26e ARM: rockchip: Add rv1108-elgin-r1 board support
Add the initial support for Elgin R1 board, which is based on the
RV1108 SoC and has the following features currently supported in
U-Boot:

- UART
- eMMC
- USB

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-16 01:30:11 +01:00
Tom Rini
401c254044 Merge branch 'master' of git://git.denx.de/u-boot-usb
- Second half of the USB Gadget DM conversion
2018-12-15 17:49:57 -05:00
Tom Rini
0dc526d98e Merge branch '2018-12-15-master-imports'
- Introduce tools-only build for host tools
- Bugfixes to poplar, syscon and the hashtable, a tee return code
- Fix a warning on gcc-8 by reworking part of mtk_image to be not unsafe
  wrt strings.
- serial_stm32 reset support
2018-12-15 17:47:28 -05:00
Kever Yang
9af1d5ef2f rockchip: rk3288-evb: dts: remove 'vmmc' from emmc node
This is a sync with kernel mainline dts.

The U-Boot eMMC does not need to care about the power for Rockchip
SoCs, because if the board is using eMMC, the power will default on
(for bootrom), so the 'vmmc', 'vqmmc' is only useful for SD in U-Boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15 20:56:46 +01:00
Christoph Muellner
1ae5cd0226 rockchip: rk3399-puma: Remove obsolete DTS node 'vcc5v0_host'.
vcc5v0_host and usbhub_enable share gpio4 RK_PA3,
which is a problem during probing (the second probe
will trigger a -EBUSY, when trying to get the gpio handle).

An analysis of the situation shows, that both regulators
are actually describing the same supply.

This patch removes the (currenlty not successful probing)
regulator vcc5v0_host from the DTS and adds the pinctrl-*
setting to usbhub_enable.

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Phiilipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-15 20:56:26 +01:00
Patrick Delaunay
de5bab9c59 syscon: update syscon_node_to_regmap to use the DM functions
+ Update the function syscon_node_to_regmap() to force bound on
  syscon uclass and directly use the list of device from DM.
+ Remove the static list syscon_list.

This patch avoid issue (crash) when syscon_node_to_regmap() is called
before and after reallocation (list content is invalid).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-12-15 11:49:56 -05:00
Andy Shevchenko
74473ed0cf tools: mtk_image: replace strncpy(d, s, sizeof(d)) with snprintf()
Starting from version 8 the GCC, i.e. C compiler, starts complaining about
possible '\0' terminator loss or, as in this case, garbage copy.

In function ‘mtk_image_set_gen_header’,
    inlined from ‘mtk_image_set_header’ at tools/mtk_image.c:733:3:
tools/mtk_image.c:659:2: warning: ‘strncpy’ specified bound 12 equals destination size [-Wstringop-truncation]
  strncpy(hdr->boot.name, bootname, sizeof(hdr->boot.name));
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In function ‘mtk_brom_parse_imagename’,
    inlined from ‘mtk_image_check_params’ at tools/mtk_image.c:388:9:
tools/mtk_image.c:325:5: warning: ‘strncpy’ specified bound 32 equals destination size [-Wstringop-truncation]
     strncpy(lk_name, val, sizeof(lk_name));
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Replace it with snprintf() to tell compiler how much room we have in the
destination buffer for source string.

Fixes: 3b975a147c ("tools: MediaTek: add MTK boot header generation to mkimage")
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2018-12-15 11:49:56 -05:00
Patrice Chotard
f828fa4d82 serial: serial_stm32: Add reset support
In some cases, UART is configured by early boot stage.
To be sure of the initial state of UART and to avoid
spurious chars on console, reset the serial block before
configuring it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-15 11:49:56 -05:00
Shawn Guo
655c6d997d poplar: fix boot failure caused by serial driver change
Commit 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various
drivers") essentially drops flag DM_FLAG_PRE_RELOC from serial_pl01x
driver for Poplar platform, because the platform falls into the
following strategy category made by the commit.

  Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Before the commit lands, Poplar platform works by statically declaring
pl011 serial device via U_BOOT_DEVICE() with DM_FLAG_PRE_RELOC flag set
in the driver.  But since Poplar also supports device configuration from
device tree, the commit practically drops the flag for Poplar, and hence
breaks the platform from booting.

This patch changes platform code and device tree to initiate pl011
serial device from device tree rather than static declaration, so that
above strategy about DM_FLAG_PRE_RELOC applies to Poplar, and therefore
the reported boot failure gets fixed.

Reported-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Fixes: 4687919684 ("serial: Remove DM_FLAG_PRE_RELOC flag in various drivers")
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-15 11:49:56 -05:00
Shawn Guo
413888a546 poplar: add a co-maintainer for poplar board
Add myself as co-maintainer for poplar board, as I'm actively working
on the board.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2018-12-15 11:49:56 -05:00
Otavio Salvador
80870e2a66 tools: add a generic config for native tools building
The motivation for this is to allow distributions to distribute all
possible tools in a generic way, avoiding the need of specific tools
building for each machine.

Especially on OpenEmbedded / Yocto Project ecosystem, it is very
common each BSP to end providing their specific tools when they need
to generate images for some SoC (e.g MX23 / MX28 in meta-freescale
case).

Using this, we can package the tools doing:

$: make tools-only_defconfig
$: make tools-only

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
[trini: Add MAINTAINERS entry for myself, add to .travis.yml, make
U-Boot itself buildable to not trip up other frameworks]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-15 11:49:56 -05:00