Merge branch 'master' of git://git.denx.de/u-boot-usb

- Second half of the USB Gadget DM conversion
This commit is contained in:
Tom Rini 2018-12-15 17:49:49 -05:00
commit 401c254044
62 changed files with 704 additions and 709 deletions

View file

@ -3,6 +3,8 @@
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
/{
ocp {
u-boot,dm-pre-reloc;

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@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
&am43xx_control_usb2phy1 {
compatible = "ti,control-phy-usb2-am437", "syscon";
};
&am43xx_control_usb2phy2 {
compatible = "ti,control-phy-usb2-am437", "syscon";
};
&ocp2scp0 {
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp", "simple-bus";
};
&ocp2scp1 {
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp", "simple-bus";
};
&dwc3_1 {
u-boot,dm-spl;
};
&usb1 {
u-boot,dm-spl;
};
&usb2_phy1 {
u-boot,dm-spl;
};
&am43xx_control_usb2phy1 {
u-boot,dm-spl;
};
&ocp2scp0 {
u-boot,dm-spl;
};

View file

@ -7,6 +7,8 @@
* Based on "dra7.dtsi"
*/
#include "am4372-u-boot.dtsi"
/{
ocp {
u-boot,dm-spl;

View file

@ -3,6 +3,8 @@
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
/{
ocp {
u-boot,dm-spl;

View file

@ -3,6 +3,8 @@
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
/{
ocp {
u-boot,dm-spl;

View file

@ -33,6 +33,34 @@
};
};
&keystone_usb0 {
status = "okay";
};
&usb0_phy {
status = "okay";
compatible = "nop-phy";
};
&usb0 {
dr_mode = "host";
status = "okay";
};
&keystone_usb1 {
status = "okay";
};
&usb1_phy {
compatible = "nop-phy";
status = "okay";
};
&usb1 {
dr_mode = "peripheral";
status = "okay";
};
&gbe0 {
phy-handle = <&ethphy0>;
};

View file

@ -201,5 +201,61 @@
status = "disabled";
clock-names = "fck";
};
usb0_phy: usb-phy@0 {
compatible = "usb-nop-xceiv";
status = "disabled";
};
keystone_usb0: keystone-dwc3@2680000 {
compatible = "ti,keystone-dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2680000 0x10000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
ranges;
dma-coherent;
dma-ranges;
status = "disabled";
/*power-domains = <&k2g_pds 0x0016>;*/
usb0: usb@2690000 {
compatible = "snps,dwc3";
reg = <0x2690000 0x10000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
maximum-speed = "high-speed";
dr_mode = "otg";
/*usb-phy = <&usb0_phy>;*/
status = "disabled";
};
};
usb1_phy: usb-phy@1 {
compatible = "usb-nop-xceiv";
status = "disabled";
};
keystone_usb1: keystone-dwc3@2580000 {
compatible = "ti,keystone-dwc3";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2580000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
ranges;
dma-coherent;
dma-ranges;
status = "disabled";
/*power-domains = <&k2g_pds 0x0017>;*/
usb1: usb@2590000 {
compatible = "snps,dwc3";
reg = <0x2590000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
maximum-speed = "high-speed";
dr_mode = "otg";
/*usb-phy = <&usb1_phy>;*/
status = "disabled";
};
};
};
};

View file

@ -7,6 +7,7 @@
#ifndef __ASM_ARM_OMAP_MUSB_H
#define __ASM_ARM_OMAP_MUSB_H
#include <linux/usb/musb.h>
extern struct musb_platform_ops musb_dsps_ops;
extern const struct musb_platform_ops am35x_ops;
@ -21,4 +22,11 @@ struct omap_musb_board_data {
};
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
struct ti_musb_platdata {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
};
#endif /* __ASM_ARM_OMAP_MUSB_H */

View file

@ -174,7 +174,55 @@ int cpu_mmc_init(bd_t *bis)
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
(!defined(CONFIG_DM_USB))
(!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
static struct ti_musb_platdata usb0 = {
.base = (void *)USB0_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
.plat = {
.config = &musb_config,
.power = 50,
.platform_ops = &musb_dsps_ops,
},
};
static struct ti_musb_platdata usb1 = {
.base = (void *)USB1_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
.plat = {
.config = &musb_config,
.power = 50,
.platform_ops = &musb_dsps_ops,
},
};
U_BOOT_DEVICES(am33xx_usbs) = {
#if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
{ "ti-musb-peripheral", &usb0 },
#elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
{ "ti-musb-host", &usb0 },
#endif
#if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
{ "ti-musb-peripheral", &usb1 },
#elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
{ "ti-musb-host", &usb1 },
#endif
};
int arch_misc_init(void)
{
return 0;
}
#else
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* USB 2.0 PHY Control */
@ -193,13 +241,6 @@ static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
}
}
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
.num_eps = 16,
.ram_bits = 12,
};
#ifdef CONFIG_AM335X_USB0
static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
{
@ -250,6 +291,7 @@ int arch_misc_init(void)
#endif
return 0;
}
#endif
#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */

View file

@ -705,6 +705,19 @@ int board_init(void)
}
#ifdef CONFIG_BOARD_LATE_INIT
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
static int device_okay(const char *path)
{
int node;
node = fdt_path_offset(gd->fdt_blob, path);
if (node < 0)
return 0;
return fdtdec_get_is_enabled(gd->fdt_blob, node);
}
#endif
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@ -717,10 +730,18 @@ int board_late_init(void)
if (get_device_type() == HS_DEVICE)
env_set("boot_fit", "1");
#endif
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
if (device_okay("/ocp/omap_dwc3@48380000"))
enable_usb_clocks(0);
if (device_okay("/ocp/omap_dwc3@483c0000"))
enable_usb_clocks(1);
#endif
return 0;
}
#endif
#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
.maximum_speed = USB_SPEED_HIGH,
@ -823,6 +844,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
return 0;
}
#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
#ifdef CONFIG_DRIVER_TI_CPSW

View file

@ -66,6 +66,18 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
int board_init(void)
{
#if CONFIG_IS_ENABLED(DM_USB)
int rc = psc_enable_module(KS2_LPSC_USB);
if (rc)
puts("Cannot enable USB0 module");
#ifdef KS2_LPSC_USB_1
rc = psc_enable_module(KS2_LPSC_USB_1);
if (rc)
puts("Cannot enable USB1 module");
#endif
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;

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@ -74,9 +74,12 @@ obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
ifdef CONFIG_SPL_USB_HOST_SUPPORT
obj-$(CONFIG_SPL_USB_SUPPORT) += usb.o usb_hub.o
obj-$(CONFIG_USB_STORAGE) += usb_storage.o
else
obj-$(CONFIG_USB_MUSB_HOST) += usb.o
endif
endif # CONFIG_SPL_BUILD

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@ -85,7 +85,9 @@ int spl_net_load_image_usb(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
bootdev->boot_device_name = "usb_ether";
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
usb_ether_init();
#endif
return spl_net_load_image(spl_image, bootdev);
}
SPL_LOAD_IMAGE_METHOD("USB eth", 0, BOOT_DEVICE_USBETH, spl_net_load_image_usb);

View file

@ -13,7 +13,11 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM33xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_ETHER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
@ -31,6 +35,7 @@ CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
@ -44,8 +49,13 @@ CONFIG_OMAP3_SPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y

View file

@ -3,6 +3,7 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
@ -12,7 +13,11 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000
@ -27,11 +32,16 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
@ -40,17 +50,25 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_OMAP_USB_PHY=y
CONFIG_USB_STORAGE=y
@ -59,3 +77,4 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y

View file

@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
@ -47,13 +48,19 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y

View file

@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
@ -40,13 +41,19 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y

View file

@ -35,7 +35,9 @@ CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
@ -50,6 +52,8 @@ CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_REMOTEPROC_TI_POWER=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
@ -57,7 +61,15 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y

View file

@ -28,7 +28,9 @@ CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
@ -43,6 +45,8 @@ CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_REMOTEPROC_TI_POWER=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
@ -50,7 +54,15 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y

View file

@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
@ -47,13 +48,19 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y

View file

@ -30,6 +30,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
@ -40,13 +41,19 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y

View file

@ -37,6 +37,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
@ -47,13 +48,19 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y

View file

@ -29,6 +29,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_TI_AEMIF=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_DAVINCI=y
@ -39,13 +40,19 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_PHY=y
CONFIG_NOP_PHY=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_DRIVER_TI_KEYSTONE_NET=y

View file

@ -47,6 +47,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
obj-$(CONFIG_SPL_USB_ETHER) += net/phy/
obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/common/
obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu/
obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/

View file

@ -164,4 +164,14 @@ config OMAP_USB2_PHY
This PHY is found on OMAP devices supporting USB2.
config KEYSTONE_USB_PHY
bool "Support TI Keystone USB PHY"
depends on PHY
depends on ARCH_KEYSTONE
help
Support for the USB PHY found on some Keystone (k2) processors
This PHY is found on some Keystone (K2) devices supporting USB.
endmenu

View file

@ -18,3 +18,4 @@ obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o
obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o

View file

@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/device.h>
#include <generic-phy.h>
#include <asm/io.h>
/* USB PHY control register offsets */
#define USB_PHY_CTL_UTMI 0x0000
#define USB_PHY_CTL_PIPE 0x0004
#define USB_PHY_CTL_PARAM_1 0x0008
#define USB_PHY_CTL_PARAM_2 0x000c
#define USB_PHY_CTL_CLOCK 0x0010
#define USB_PHY_CTL_PLL 0x0014
#define PHY_OTG_VBUSVLDECTSEL BIT(16)
#define PHY_REF_SSP_EN BIT(29)
struct keystone_usb_phy {
void __iomem *reg;
};
static int keystone_usb_init(struct phy *phy)
{
u32 val;
struct udevice *dev = phy->dev;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
/*
* VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
* It should always be cleared because our USB PHY has an onchip VBUS
* analog comparator.
*/
val = readl(keystone->reg + USB_PHY_CTL_CLOCK);
/* quit selecting the vbusvldextsel by default! */
val &= ~PHY_OTG_VBUSVLDECTSEL;
writel(val, keystone->reg + USB_PHY_CTL_CLOCK);
return 0;
}
static int keystone_usb_power_on(struct phy *phy)
{
u32 val;
struct udevice *dev = phy->dev;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
val = readl(keystone->reg + USB_PHY_CTL_CLOCK);
val |= PHY_REF_SSP_EN;
writel(val, keystone->reg + USB_PHY_CTL_CLOCK);
return 0;
}
static int keystone_usb_power_off(struct phy *phy)
{
u32 val;
struct udevice *dev = phy->dev;
struct keystone_usb_phy *keystone = dev_get_priv(dev);
val = readl(keystone->reg + USB_PHY_CTL_CLOCK);
val &= ~PHY_REF_SSP_EN;
writel(val, keystone->reg + USB_PHY_CTL_CLOCK);
return 0;
}
static int keystone_usb_exit(struct phy *phy)
{
return 0;
}
static int keystone_usb_phy_probe(struct udevice *dev)
{
struct keystone_usb_phy *keystone = dev_get_priv(dev);
keystone->reg = dev_remap_addr_index(dev, 0);
if (!keystone->reg) {
pr_err("unable to remap usb phy\n");
return -EINVAL;
}
return 0;
}
static const struct udevice_id keystone_usb_phy_ids[] = {
{ .compatible = "ti,keystone-usbphy" },
{ }
};
static struct phy_ops keystone_usb_phy_ops = {
.init = keystone_usb_init,
.power_on = keystone_usb_power_on,
.power_off = keystone_usb_power_off,
.exit = keystone_usb_exit,
};
U_BOOT_DRIVER(keystone_usb_phy) = {
.name = "keystone_usb_phy",
.id = UCLASS_PHY,
.of_match = keystone_usb_phy_ids,
.ops = &keystone_usb_phy_ops,
.probe = keystone_usb_phy_probe,
.priv_auto_alloc_size = sizeof(struct keystone_usb_phy),
};

View file

@ -19,6 +19,11 @@
#define OMAP_DEV_PHY_PD BIT(0)
#define OMAP_USB2_PHY_PD BIT(28)
#define AM437X_USB2_PHY_PD BIT(0)
#define AM437X_USB2_OTG_PD BIT(1)
#define AM437X_USB2_OTGVDET_EN BIT(19)
#define AM437X_USB2_OTGSESSEND_EN BIT(20)
#define USB2PHY_DISCON_BYP_LATCH BIT(31)
#define USB2PHY_ANA_CONFIG1 (0x4c)
@ -60,6 +65,15 @@ static const struct usb_phy_data dra7x_usb2_phy2_data = {
.power_off = OMAP_USB2_PHY_PD,
};
static const struct usb_phy_data am437x_usb2_data = {
.label = "am437x_usb2",
.flags = 0,
.mask = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD |
AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN,
.power_on = AM437X_USB2_OTGVDET_EN | AM437X_USB2_OTGSESSEND_EN,
.power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD,
};
static const struct udevice_id omap_usb2_id_table[] = {
{
.compatible = "ti,omap5-usb2",
@ -73,6 +87,10 @@ static const struct udevice_id omap_usb2_id_table[] = {
.compatible = "ti,dra7x-usb2-phy2",
.data = (ulong)&dra7x_usb2_phy2_data,
},
{
.compatible = "ti,am437x-usb2",
.data = (ulong)&am437x_usb2_data,
},
{},
};
@ -170,20 +188,25 @@ int omap_usb2_phy_probe(struct udevice *dev)
}
regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-phy-power");
if (IS_ERR(regmap)) {
printf("can't get regmap (err %ld)\n", PTR_ERR(regmap));
return PTR_ERR(regmap);
if (!IS_ERR(regmap)) {
priv->pwr_regmap = regmap;
rc = dev_read_u32_array(dev, "syscon-phy-power", tmp, 2);
if (rc) {
printf("couldn't get power reg. offset (err %d)\n", rc);
return rc;
}
priv->pwr_reg_offset = tmp[1];
return 0;
}
priv->pwr_regmap = regmap;
rc = dev_read_u32_array(dev, "syscon-phy-power", tmp, 2);
if (rc) {
printf("couldn't get power reg. offset (err %d)\n", rc);
return rc;
regmap = syscon_regmap_lookup_by_phandle(dev, "ctrl-module");
if (!IS_ERR(regmap)) {
priv->pwr_regmap = regmap;
priv->pwr_reg_offset = 0;
return 0;
}
priv->pwr_reg_offset = tmp[1];
return 0;
printf("can't get regmap (err %ld)\n", PTR_ERR(regmap));
return PTR_ERR(regmap);
}
U_BOOT_DRIVER(omap_usb2_phy) = {

View file

@ -49,7 +49,7 @@ config DM_USB
config SPL_DM_USB
bool "Enable driver model for USB in SPL"
depends on DM_USB
depends on SPL_DM && DM_USB
default y
config DM_USB_GADGET

View file

@ -342,7 +342,9 @@ static int dwc3_glue_remove(struct udevice *dev)
static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "xlnx,zynqmp-dwc3" },
{ .compatible = "ti,keystone-dwc3"},
{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
{ }
};

View file

@ -16,7 +16,6 @@
#include <common.h>
#include <malloc.h>
#include <asm/dma-mapping.h>
#include <usb/lin_gadget_compat.h>
#include <linux/bug.h>
#include <linux/list.h>

View file

@ -19,7 +19,6 @@
#include <common.h>
#include <malloc.h>
#include <ti-usb-phy-uboot.h>
#include <usb/lin_gadget_compat.h>
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>

View file

@ -10,7 +10,6 @@
#include <malloc.h>
#include <memalign.h>
#include <usb.h>
#include <usb/lin_gadget_compat.h>
#include <linux/mii.h>
#include <linux/bitops.h>
#include "usb_ether.h"

View file

@ -24,7 +24,6 @@
#include <linux/usb/gadget.h>
#include <linux/usb/at91_udc.h>
#include <malloc.h>
#include <usb/lin_gadget_compat.h>
#include "at91_udc.h"

View file

@ -16,7 +16,6 @@
#include <linux/usb/gadget.h>
#include <linux/usb/atmel_usba_udc.h>
#include <malloc.h>
#include <usb/lin_gadget_compat.h>
#include "atmel_usba_udc.h"

View file

@ -735,8 +735,21 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
case USB_DT_DEVICE:
cdev->desc.bNumConfigurations =
count_configs(cdev, USB_DT_DEVICE);
cdev->desc.bMaxPacketSize0 =
cdev->gadget->ep0->maxpacket;
/*
* If the speed is Super speed, then the supported
* max packet size is 512 and it should be sent as
* exponent of 2. So, 9(2^9=512) should be filled in
* bMaxPacketSize0. Also fill USB version as 3.0
* if speed is Super speed.
*/
if (cdev->gadget->speed == USB_SPEED_SUPER) {
cdev->desc.bMaxPacketSize0 = 9;
cdev->desc.bcdUSB = cpu_to_le16(0x0300);
} else {
cdev->desc.bMaxPacketSize0 =
cdev->gadget->ep0->maxpacket;
}
value = min(w_length, (u16) sizeof cdev->desc);
memcpy(req->buf, &cdev->desc, value);
break;

View file

@ -33,7 +33,6 @@
#include "dwc2_udc_otg_regs.h"
#include "dwc2_udc_otg_priv.h"
#include <usb/lin_gadget_compat.h>
/***********************************************************/

View file

@ -33,7 +33,6 @@
#include "dwc2_udc_otg_regs.h"
#include "dwc2_udc_otg_priv.h"
#include <usb/lin_gadget_compat.h>
#include <usb/dwc2_udc.h>

View file

@ -12,7 +12,6 @@
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/list.h>
#include <usb/lin_gadget_compat.h>
#include <usb/dwc2_udc.h>
/*-------------------------------------------------------------------------*/

View file

@ -256,7 +256,7 @@
#include <linux/usb/gadget.h>
#include <linux/usb/gadget.h>
#include <linux/usb/composite.h>
#include <usb/lin_gadget_compat.h>
#include <linux/bitmap.h>
#include <g_dnl.h>
/*------------------------------------------------------------------------*/

View file

@ -100,6 +100,7 @@ struct f_sdp {
enum sdp_state state;
enum sdp_state next_state;
u32 dnl_address;
u32 dnl_bytes;
u32 dnl_bytes_remaining;
u32 jmp_address;
bool always_send_status;
@ -276,6 +277,7 @@ static void sdp_rx_command_complete(struct usb_ep *ep, struct usb_request *req)
sdp->state = SDP_STATE_RX_FILE_DATA;
sdp->dnl_address = be32_to_cpu(cmd->addr);
sdp->dnl_bytes_remaining = be32_to_cpu(cmd->cnt);
sdp->dnl_bytes = sdp->dnl_bytes_remaining;
sdp->next_state = SDP_STATE_IDLE;
printf("Downloading file of size %d to 0x%08x... ",
@ -355,6 +357,9 @@ static void sdp_rx_data_complete(struct usb_ep *ep, struct usb_request *req)
if (sdp->dnl_bytes_remaining)
return;
#ifndef CONFIG_SPL_BUILD
env_set_hex("filesize", sdp->dnl_bytes);
#endif
printf("done\n");
switch (sdp->state) {

View file

@ -29,7 +29,6 @@
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <usb/lin_gadget_compat.h>
#include <asm/arch/pxa-regs.h>
#include "pxa25x_udc.h"

View file

@ -50,7 +50,6 @@ obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o

View file

@ -1,240 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* USB 3.0 DRD Controller
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*/
#include <common.h>
#include <watchdog.h>
#include <usb.h>
#include <asm/arch/psc_defs.h>
#include <asm/io.h>
#include <linux/usb/dwc3.h>
#include <asm/arch/xhci-keystone.h>
#include <linux/errno.h>
#include <linux/list.h>
#include "xhci.h"
struct kdwc3_irq_regs {
u32 revision; /* 0x000 */
u32 rsvd0[3];
u32 sysconfig; /* 0x010 */
u32 rsvd1[1];
u32 irq_eoi;
u32 rsvd2[1];
struct {
u32 raw_status;
u32 status;
u32 enable_set;
u32 enable_clr;
} irqs[16];
};
struct keystone_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
struct xhci_hcor *hcor;
struct kdwc3_irq_regs *usbss;
struct keystone_xhci_phy *phy;
};
struct keystone_xhci keystone;
static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy)
{
u32 val;
/*
* VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
* It should always be cleared because our USB PHY has an onchip VBUS
* analog comparator.
*/
val = readl(&phy->phy_clock);
/* quit selecting the vbusvldextsel by default! */
val &= ~USB3_PHY_OTG_VBUSVLDECTSEL;
writel(val, &phy->phy_clock);
}
static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
{
u32 val;
/* Disable the PHY REFCLK clock gate */
val = readl(&phy->phy_clock);
val &= ~USB3_PHY_REF_SSP_EN;
writel(val, &phy->phy_clock);
}
static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
{
int ret;
ret = dwc3_core_init(dwc3_reg);
if (ret) {
debug("failed to initialize core\n");
return -EINVAL;
}
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
return 0;
}
int xhci_hcd_init(int index,
struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
{
u32 val;
int ret;
struct xhci_hccr *hcd;
struct xhci_hcor *hcor;
struct kdwc3_irq_regs *usbss;
struct keystone_xhci_phy *phy;
usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
/* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
val = readl(&(phy->phy_clock));
val |= USB3_PHY_REF_SSP_EN;
writel(val, &phy->phy_clock);
mdelay(100);
/* Release USB from reset */
ret = psc_enable_module(KS2_LPSC_USB);
if (ret) {
puts("Cannot enable USB module");
return -1;
}
mdelay(100);
/* Initialize usb phy */
keystone_xhci_phy_set(phy);
/* soft reset usbss */
writel(1, &usbss->sysconfig);
while (readl(&usbss->sysconfig) & 1)
;
val = readl(&usbss->revision);
debug("usbss revision %x\n", val);
/* Initialize usb core */
hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
DWC3_REG_OFFSET);
keystone_xhci_core_init(keystone.dwc3_reg);
/* set register addresses */
hcor = (struct xhci_hcor *)((uint32_t)hcd +
HC_LENGTH(readl(&hcd->cr_capbase)));
debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
(u32)hcd, (u32)hcor,
(u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
keystone.usbss = usbss;
keystone.phy = phy;
keystone.hcd = hcd;
keystone.hcor = hcor;
*ret_hccr = hcd;
*ret_hcor = hcor;
return 0;
}
static int keystone_xhci_phy_suspend(void)
{
int loop_cnt = 0;
struct xhci_hcor *hcor;
uint32_t *portsc_1 = NULL;
uint32_t *portsc_2 = NULL;
u32 val, usb2_pls, usb3_pls, event_q;
struct dwc3 *dwc3_reg = keystone.dwc3_reg;
/* set register addresses */
hcor = keystone.hcor;
/* Bypass Scrambling and Set Shorter Training sequence for simulation */
val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2);
writel(val, &dwc3_reg->g_ctl);
/* GUSB2PHYCFG */
val = readl(&dwc3_reg->g_usb2phycfg[0]);
/* assert bit 6 (SusPhy) */
val |= DWC3_GUSB2PHYCFG_SUSPHY;
writel(val, &dwc3_reg->g_usb2phycfg[0]);
/* GUSB3PIPECTL */
val = readl(&dwc3_reg->g_usb3pipectl[0]);
/*
* assert bit 29 to allow PHY to go to suspend when idle
* and cause the USB3 SS PHY to enter suspend mode
*/
val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY);
writel(val, &dwc3_reg->g_usb3pipectl[0]);
/*
* Steps necessary to allow controller to suspend even when
* VBUS is HIGH:
* - Init DCFG[2:0] (DevSpd) to: 1=FS
* - Init GEVNTADR0 to point to an eventQ
* - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ
* - Init DCTL::Run_nStop = 1
*/
writel(0x00020001, &dwc3_reg->d_cfg);
/* TODO: local2global( (Uint32) eventQ )? */
writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo);
writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi);
writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz);
/* Run */
writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl);
mdelay(100);
/* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */
portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc);
portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc);
usb2_pls = 0;
usb3_pls = 0;
do {
++loop_cnt;
usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5;
usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5;
} while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000);
if (usb2_pls != 0x4 || usb3_pls != 0x4) {
debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n",
usb2_pls, usb3_pls);
return -1;
}
debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt);
return 0;
}
void xhci_hcd_stop(int index)
{
/* Disable USB */
if (keystone_xhci_phy_suspend())
return;
if (psc_disable_module(KS2_LPSC_USB)) {
debug("PSC disable module USB failed!\n");
return;
}
/* Disable PHY */
keystone_xhci_phy_unset(keystone.phy);
/* memset(&keystone, 0, sizeof(struct keystone_xhci)); */
debug("xhci_hcd_stop OK.\n");
}

View file

@ -406,7 +406,7 @@ static int am35x_musb_init(struct musb *musb)
musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 1);
msleep(5);
@ -437,7 +437,7 @@ static int am35x_musb_exit(struct musb *musb)
#endif
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 0);
#ifndef __UBOOT__
@ -628,7 +628,7 @@ static int am35x_suspend(struct device *dev)
struct omap_musb_board_data *data = plat->board_data;
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 0);
clk_disable(glue->phy_clk);
@ -645,7 +645,7 @@ static int am35x_resume(struct device *dev)
int ret;
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 1);
ret = clk_enable(glue->phy_clk);

View file

@ -450,7 +450,7 @@ static int dsps_musb_init(struct musb *musb)
dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 1);
musb->isr = dsps_interrupt;
@ -491,7 +491,7 @@ static int dsps_musb_exit(struct musb *musb)
#endif
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 0);
#ifndef __UBOOT__
@ -691,7 +691,7 @@ static int dsps_suspend(struct device *dev)
struct omap_musb_board_data *data = plat->board_data;
/* Shutdown the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 0);
return 0;
@ -703,7 +703,7 @@ static int dsps_resume(struct device *dev)
struct omap_musb_board_data *data = plat->board_data;
/* Start the on-chip PHY and its PLL. */
if (data->set_phy_power)
if (data && data->set_phy_power)
data->set_phy_power(data->dev, 1);
return 0;

View file

@ -1775,6 +1775,14 @@ static int musb_gadget_start(struct usb_gadget *g,
struct usb_gadget_driver *driver);
static int musb_gadget_stop(struct usb_gadget *g,
struct usb_gadget_driver *driver);
#else
static int musb_gadget_stop(struct usb_gadget *g)
{
struct musb *musb = gadget_to_musb(g);
musb_stop(musb);
return 0;
}
#endif
static const struct usb_gadget_ops musb_gadget_operations = {
@ -1787,6 +1795,9 @@ static const struct usb_gadget_ops musb_gadget_operations = {
#ifndef __UBOOT__
.udc_start = musb_gadget_start,
.udc_stop = musb_gadget_stop,
#else
.udc_start = musb_gadget_start,
.udc_stop = musb_gadget_stop,
#endif
};

View file

@ -367,7 +367,7 @@ struct dm_usb_ops musb_usb_ops = {
#endif /* CONFIG_IS_ENABLED(DM_USB) */
#endif /* CONFIG_USB_MUSB_HOST */
#ifdef CONFIG_USB_MUSB_GADGET
#if defined(CONFIG_USB_MUSB_GADGET) && !CONFIG_IS_ENABLED(DM_USB_GADGET)
static struct musb *gadget;
int usb_gadget_handle_interrupts(int index)
@ -430,7 +430,7 @@ struct musb *musb_register(struct musb_hdrc_platform_data *plat, void *bdata,
musbp = &musb_host.host;
break;
#endif
#ifdef CONFIG_USB_MUSB_GADGET
#if defined(CONFIG_USB_MUSB_GADGET) && !CONFIG_IS_ENABLED(DM_USB_GADGET)
case MUSB_PERIPHERAL:
musbp = &gadget;
break;

View file

@ -435,11 +435,14 @@ static int musb_usb_probe(struct udevice *dev)
{
struct sunxi_glue *glue = dev_get_priv(dev);
struct musb_host_data *host = &glue->mdata;
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct musb_hdrc_platform_data pdata;
void *base = dev_read_addr_ptr(dev);
int ret;
#ifdef CONFIG_USB_MUSB_HOST
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
#endif
if (!base)
return -EINVAL;
@ -459,7 +462,6 @@ static int musb_usb_probe(struct udevice *dev)
return ret;
}
priv->desc_before_addr = true;
memset(&pdata, 0, sizeof(pdata));
pdata.power = 250;
@ -467,6 +469,8 @@ static int musb_usb_probe(struct udevice *dev)
pdata.config = glue->cfg->config;
#ifdef CONFIG_USB_MUSB_HOST
priv->desc_before_addr = true;
pdata.mode = MUSB_HOST;
host->host = musb_init_controller(&pdata, &glue->dev, base);
if (!host->host)

View file

@ -20,22 +20,33 @@
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(DM_USB)
/* USB 2.0 PHY Control */
#define CM_PHY_PWRDN (1 << 0)
#define CM_PHY_OTG_PWRDN (1 << 1)
#define OTGVDET_EN (1 << 19)
#define OTGSESSENDEN (1 << 20)
#define AM335X_USB0_CTRL 0x0
#define AM335X_USB1_CTRL 0x8
struct ti_musb_platdata {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
struct musb_hdrc_config musb_config;
struct omap_musb_board_data otg_board_data;
};
static void ti_musb_set_phy_power(struct udevice *dev, u8 on)
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
if (!platdata->ctrl_mod_base)
return;
if (on) {
clrsetbits_le32(platdata->ctrl_mod_base,
CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
OTGVDET_EN | OTGSESSENDEN);
} else {
clrsetbits_le32(platdata->ctrl_mod_base, 0,
CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
}
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int ti_musb_get_usb_index(int node)
{
@ -64,20 +75,6 @@ static int ti_musb_get_usb_index(int node)
return -ENOENT;
}
static void ti_musb_set_phy_power(struct udevice *dev, u8 on)
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
if (on) {
clrsetbits_le32(platdata->ctrl_mod_base,
CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
OTGVDET_EN | OTGSESSENDEN);
} else {
clrsetbits_le32(platdata->ctrl_mod_base, 0,
CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
}
}
static int ti_musb_ofdata_to_platdata(struct udevice *dev)
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
@ -86,6 +83,7 @@ static int ti_musb_ofdata_to_platdata(struct udevice *dev)
int phys;
int ctrl_mod;
int usb_index;
struct musb_hdrc_config *musb_config;
platdata->base = (void *)devfdt_get_addr_index(dev, 1);
@ -96,38 +94,41 @@ static int ti_musb_ofdata_to_platdata(struct udevice *dev)
switch (usb_index) {
case 1:
platdata->ctrl_mod_base += AM335X_USB1_CTRL;
break;
case 0:
platdata->ctrl_mod_base += AM335X_USB0_CTRL;
break;
default:
break;
}
platdata->musb_config.multipoint = fdtdec_get_int(fdt, node,
"mentor,multipoint",
-1);
if (platdata->musb_config.multipoint < 0) {
musb_config = malloc(sizeof(struct musb_hdrc_config));
memset(musb_config, 0, sizeof(struct musb_hdrc_config));
musb_config->multipoint = fdtdec_get_int(fdt, node,
"mentor,multipoint", -1);
if (musb_config->multipoint < 0) {
pr_err("MUSB multipoint DT entry missing\n");
return -ENOENT;
}
platdata->musb_config.dyn_fifo = 1;
musb_config->dyn_fifo = 1;
platdata->musb_config.num_eps = fdtdec_get_int(fdt, node,
"mentor,num-eps", -1);
if (platdata->musb_config.num_eps < 0) {
musb_config->num_eps = fdtdec_get_int(fdt, node, "mentor,num-eps",
-1);
if (musb_config->num_eps < 0) {
pr_err("MUSB num-eps DT entry missing\n");
return -ENOENT;
}
platdata->musb_config.ram_bits = fdtdec_get_int(fdt, node,
"mentor,ram-bits", -1);
if (platdata->musb_config.ram_bits < 0) {
musb_config->ram_bits = fdtdec_get_int(fdt, node, "mentor,ram-bits",
-1);
if (musb_config->ram_bits < 0) {
pr_err("MUSB ram-bits DT entry missing\n");
return -ENOENT;
}
platdata->otg_board_data.set_phy_power = ti_musb_set_phy_power;
platdata->otg_board_data.dev = dev;
platdata->plat.config = &platdata->musb_config;
platdata->plat.config = musb_config;
platdata->plat.power = fdtdec_get_int(fdt, node, "mentor,power", -1);
if (platdata->plat.power < 0) {
@ -136,29 +137,27 @@ static int ti_musb_ofdata_to_platdata(struct udevice *dev)
}
platdata->plat.platform_ops = &musb_dsps_ops;
platdata->plat.board_data = &platdata->otg_board_data;
return 0;
}
#endif
static int ti_musb_host_probe(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct omap_musb_board_data *otg_board_data;
int ret;
priv->desc_before_addr = true;
otg_board_data = &platdata->otg_board_data;
host->host = musb_init_controller(&platdata->plat,
(struct device *)otg_board_data,
NULL,
platdata->base);
if (!host->host)
return -EIO;
ti_musb_set_phy_power(dev, 1);
ret = musb_lowlevel_init(host);
return ret;
@ -169,10 +168,12 @@ static int ti_musb_host_remove(struct udevice *dev)
struct musb_host_data *host = dev_get_priv(dev);
musb_stop(host->host);
ti_musb_set_phy_power(dev, 0);
return 0;
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int ti_musb_host_ofdata_to_platdata(struct udevice *dev)
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
@ -190,11 +191,14 @@ static int ti_musb_host_ofdata_to_platdata(struct udevice *dev)
return 0;
}
#endif
U_BOOT_DRIVER(ti_musb_host) = {
.name = "ti-musb-host",
.id = UCLASS_USB,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.ofdata_to_platdata = ti_musb_host_ofdata_to_platdata,
#endif
.probe = ti_musb_host_probe,
.remove = ti_musb_host_remove,
.ops = &musb_usb_ops,
@ -202,6 +206,82 @@ U_BOOT_DRIVER(ti_musb_host) = {
.priv_auto_alloc_size = sizeof(struct musb_host_data),
};
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
struct ti_musb_peripheral {
struct musb *periph;
};
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int ti_musb_peripheral_ofdata_to_platdata(struct udevice *dev)
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
int ret;
ret = ti_musb_ofdata_to_platdata(dev);
if (ret) {
pr_err("platdata dt parse error\n");
return ret;
}
platdata->plat.mode = MUSB_PERIPHERAL;
return 0;
}
#endif
int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
struct ti_musb_peripheral *priv = dev_get_priv(dev);
priv->periph->isr(0, priv->periph);
return 0;
}
static int ti_musb_peripheral_probe(struct udevice *dev)
{
struct ti_musb_peripheral *priv = dev_get_priv(dev);
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
int ret;
priv->periph = musb_init_controller(&platdata->plat,
NULL,
platdata->base);
if (!priv->periph)
return -EIO;
ti_musb_set_phy_power(dev, 1);
musb_gadget_setup(priv->periph);
return usb_add_gadget_udc((struct device *)dev, &priv->periph->g);
}
static int ti_musb_peripheral_remove(struct udevice *dev)
{
struct ti_musb_peripheral *priv = dev_get_priv(dev);
usb_del_gadget_udc(&priv->periph->g);
ti_musb_set_phy_power(dev, 0);
return 0;
}
U_BOOT_DRIVER(ti_musb_peripheral) = {
.name = "ti-musb-peripheral",
.id = UCLASS_USB_GADGET_GENERIC,
#if CONFIG_IS_ENABLED(OF_CONTROL)
.ofdata_to_platdata = ti_musb_peripheral_ofdata_to_platdata,
#endif
.probe = ti_musb_peripheral_probe,
.remove = ti_musb_peripheral_remove,
.ops = &musb_usb_ops,
.platdata_auto_alloc_size = sizeof(struct ti_musb_platdata),
.priv_auto_alloc_size = sizeof(struct ti_musb_peripheral),
.flags = DM_FLAG_PRE_RELOC,
};
#endif
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int ti_musb_wrapper_bind(struct udevice *parent)
{
const void *fdt = gd->fdt_blob;
@ -222,15 +302,23 @@ static int ti_musb_wrapper_bind(struct udevice *parent)
switch (dr_mode) {
case USB_DR_MODE_PERIPHERAL:
/* Bind MUSB device */
ret = device_bind_driver_to_node(parent,
"ti-musb-peripheral",
name,
offset_to_ofnode(node),
&dev);
if (ret)
pr_err("musb - not able to bind usb peripheral node\n");
break;
case USB_DR_MODE_HOST:
/* Bind MUSB host */
ret = device_bind_driver_to_node(parent, "ti-musb-host",
name, offset_to_ofnode(node), &dev);
if (ret) {
ret = device_bind_driver_to_node(parent,
"ti-musb-host",
name,
offset_to_ofnode(node),
&dev);
if (ret)
pr_err("musb - not able to bind usb host node\n");
return ret;
}
break;
default:
break;
@ -250,5 +338,6 @@ U_BOOT_DRIVER(ti_musb_wrapper) = {
.of_match = ti_musb_ids,
.bind = ti_musb_wrapper_bind,
};
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
#endif /* CONFIG_IS_ENABLED(DM_USB) */

View file

@ -11,17 +11,10 @@ config USB_MUSB_HCD
config USB_MUSB_UDC
bool "Legacy USB Device Controller"
config USB_DAVINCI
bool "Legacy MUSB DaVinci"
config USB_OMAP3
bool "Legacy MUSB OMAP3 / OMAP4"
depends on ARCH_OMAP2PLUS
config USB_DA8XX
bool "Legacy MUSB DA8xx/OMAP-L1x"
depends on ARCH_DAVINCI
config USB_AM35X
bool"Legacy MUSB AM35x"
depends on ARCH_OMAP2PLUS && !USB_OMAP3

View file

@ -5,7 +5,5 @@
obj-$(CONFIG_USB_MUSB_HCD) += musb_hcd.o musb_core.o
obj-$(CONFIG_USB_MUSB_UDC) += musb_udc.o musb_core.o
obj-$(CONFIG_USB_DAVINCI) += davinci.o
obj-$(CONFIG_USB_OMAP3) += omap3.o
obj-$(CONFIG_USB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_AM35X) += am35x.o

View file

@ -1,127 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* da8xx.c - TI's DA8xx platform specific usb wrapper functions.
*
* Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
*
* Based on drivers/usb/musb/davinci.c
*
* Copyright (C) 2009 Texas Instruments Incorporated
*/
#include <common.h>
#include "musb_core.h"
#include <asm/arch/da8xx-usb.h>
/* MUSB platform configuration */
struct musb_config musb_cfg = {
.regs = (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE,
.timeout = DA8XX_USB_OTG_TIMEOUT,
.musb_speed = 0,
};
/*
* This function enables VBUS by driving the GPIO Bank4 Pin 15 high.
*/
static void enable_vbus(void)
{
u32 value;
/* configure GPIO bank4 pin 15 in output direction */
value = readl(&davinci_gpio_bank45->dir);
writel((value & (~DA8XX_USB_VBUS_GPIO)), &davinci_gpio_bank45->dir);
/* set GPIO bank4 pin 15 high to drive VBUS */
value = readl(&davinci_gpio_bank45->set_data);
writel((value | DA8XX_USB_VBUS_GPIO), &davinci_gpio_bank45->set_data);
}
/*
* Enable the usb0 phy. This initialization procedure is explained in
* the DA8xx USB user guide document.
*/
static u8 phy_on(void)
{
u32 timeout;
u32 cfgchip2;
cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ);
cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
CFGCHIP2_REFFREQ_24MHZ;
writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
/* wait until the usb phy pll locks */
timeout = musb_cfg.timeout;
while (timeout--)
if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
return 1;
/* USB phy was not turned on */
return 0;
}
/*
* Disable the usb phy
*/
static void phy_off(void)
{
u32 cfgchip2;
/*
* Power down the on-chip PHY.
*/
cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
cfgchip2 &= ~CFGCHIP2_PHY_PLLON;
cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
}
/*
* This function performs DA8xx platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
u32 revision;
/* enable psc for usb2.0 */
lpsc_on(33);
/* enable usb vbus */
enable_vbus();
/* reset the controller */
writel(0x1, &da8xx_usb_regs->control);
udelay(5000);
/* start the on-chip usb phy and its pll */
if (phy_on() == 0)
return -1;
/* Returns zero if e.g. not clocked */
revision = readl(&da8xx_usb_regs->revision);
if (revision == 0)
return -1;
/* Disable all interrupts */
writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
return 0;
}
/*
* This function performs DA8xx platform specific deinitialization for usb0.
*/
void musb_platform_deinit(void)
{
/* Turn of the phy */
phy_off();
/* flush any interrupts */
writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
writel(0, &da8xx_usb_regs->eoi);
}

View file

@ -1,123 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* TI's Davinci platform specific USB wrapper functions.
*
* Copyright (c) 2008 Texas Instruments
*
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*/
#include <common.h>
#include <asm/io.h>
#include "davinci.h"
#include <asm/arch/hardware.h>
#if !defined(CONFIG_DV_USBPHY_CTL)
#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN)
#endif
/* MUSB platform configuration */
struct musb_config musb_cfg = {
.regs = (struct musb_regs *)MENTOR_USB0_BASE,
.timeout = DAVINCI_USB_TIMEOUT,
.musb_speed = 0,
};
/* MUSB module register overlay */
struct davinci_usb_regs *dregs;
/*
* Enable the USB phy
*/
static u8 phy_on(void)
{
u32 timeout;
#ifdef DAVINCI_DM365EVM
u32 val;
#endif
/* Wait until the USB phy is turned on */
#ifdef DAVINCI_DM365EVM
writel(USBPHY_PHY24MHZ | USBPHY_SESNDEN |
USBPHY_VBDTCTEN, USBPHY_CTL_PADDR);
#else
writel(CONFIG_DV_USBPHY_CTL, USBPHY_CTL_PADDR);
#endif
timeout = musb_cfg.timeout;
#ifdef DAVINCI_DM365EVM
/* Set the ownership of GIO33 to USB */
val = readl(PINMUX4);
val &= ~(PINMUX4_USBDRVBUS_BITCLEAR);
val |= PINMUX4_USBDRVBUS_BITSET;
writel(val, PINMUX4);
#endif
while (timeout--)
if (readl(USBPHY_CTL_PADDR) & USBPHY_PHYCLKGD)
return 1;
/* USB phy was not turned on */
return 0;
}
/*
* Disable the USB phy
*/
static void phy_off(void)
{
/* powerdown the on-chip PHY and its oscillator */
writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR);
}
void __enable_vbus(void)
{
/*
* nothing to do, vbus is handled through the cpu.
* Define this function in board code, if it is
* different on your board.
*/
}
void enable_vbus(void)
__attribute__((weak, alias("__enable_vbus")));
/*
* This function performs Davinci platform specific initialization for usb0.
*/
int musb_platform_init(void)
{
u32 revision;
/* enable USB VBUS */
enable_vbus();
/* start the on-chip USB phy and its pll */
if (!phy_on())
return -1;
/* reset the controller */
dregs = (struct davinci_usb_regs *)DAVINCI_USB0_BASE;
writel(1, &dregs->ctrlr);
udelay(5000);
/* Returns zero if e.g. not clocked */
revision = readl(&dregs->version);
if (!revision)
return -1;
/* Disable all interrupts */
writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_RXINT_MASK |
DAVINCI_USB_TXINT_MASK , &dregs->intmsksetr);
return 0;
}
/*
* This function performs Davinci platform specific deinitialization for usb0.
*/
void musb_platform_deinit(void)
{
/* Turn of the phy */
phy_off();
/* flush any interrupts */
writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_TXINT_MASK |
DAVINCI_USB_RXINT_MASK , &dregs->intclrr);
}

View file

@ -1,73 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* TI's Davinci platform specific USB wrapper functions.
*
* Copyright (c) 2008 Texas Instruments
*
* Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
*/
#ifndef __DAVINCI_USB_H__
#define __DAVINCI_USB_H__
#include <asm/arch/hardware.h>
#include "musb_core.h"
/* Base address of DAVINCI usb0 wrapper */
#define DAVINCI_USB0_BASE 0x01C64000
/* Base address of DAVINCI musb core */
#define MENTOR_USB0_BASE (DAVINCI_USB0_BASE+0x400)
/*
* Davinci platform USB wrapper register overlay. Note: Only the required
* registers are included in this structure. It can be expanded as required.
*/
struct davinci_usb_regs {
u32 version;
u32 ctrlr;
u32 reserved[0x20];
u32 intclrr;
u32 intmskr;
u32 intmsksetr;
};
#define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
#define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
#define DAVINCI_USB_USBINT_SHIFT 16
#define DAVINCI_USB_TXINT_SHIFT 0
#define DAVINCI_USB_RXINT_SHIFT 8
#define DAVINCI_INTR_DRVVBUS 0x0100
#define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
#define DAVINCI_USB_TXINT_MASK \
(DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT)
#define DAVINCI_USB_RXINT_MASK \
(DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT)
#define MGC_BUSCTL_OFFSET(_bEnd, _bOffset) \
(0x80 + (8*(_bEnd)) + (_bOffset))
/* Integrated highspeed/otg PHY */
#define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34)
#define USBPHY_PHY24MHZ (1 << 13)
#define USBPHY_PHYCLKGD (1 << 8)
#define USBPHY_SESNDEN (1 << 7) /* v(sess_end) comparator */
#define USBPHY_VBDTCTEN (1 << 6) /* v(bus) comparator */
#define USBPHY_PHYPLLON (1 << 4) /* override pll suspend */
#define USBPHY_CLKO1SEL (1 << 3)
#define USBPHY_OSCPDWN (1 << 2)
#define USBPHY_PHYPDWN (1 << 0)
/* Timeout for Davinci USB module */
#define DAVINCI_USB_TIMEOUT 0x3FFFFFF
/* IO Expander I2C address and VBUS enable mask */
#define IOEXP_I2C_ADDR 0x3A
#define IOEXP_VBUSEN_MASK 1
/* extern functions */
extern void lpsc_on(unsigned int id);
extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
extern void enable_vbus(void);
#endif /* __DAVINCI_USB_H__ */

View file

@ -46,8 +46,6 @@
#include "omap3.h"
#elif defined(CONFIG_USB_AM35X)
#include "am35x.h"
#elif defined(CONFIG_USB_DAVINCI)
#include "davinci.h"
#endif
/* Define MUSB_DEBUG for debugging */

View file

@ -253,7 +253,6 @@
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
#undef CONFIG_DM_USB
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)

View file

@ -169,12 +169,16 @@
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
#define DFU_ALT_INFO_MMC \
"dfu_alt_info_mmc=" \
"MLO fat 0 1;" \
"u-boot.img fat 0 1;" \
"uEnv.txt fat 0 1\0"
/* DFU settings */
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
/* U-Boot general configuration */
#define CONFIG_MX_CYCLIC
@ -214,6 +218,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
DFUARGS \
"bootdir=/boot\0" \
"tftp_root=/\0" \
"nfs_root=/export\0" \

23
include/linux/bitmap.h Normal file
View file

@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0+
#ifndef __LINUX_BITMAP_H
#define __LINUX_BITMAP_H
#include <asm/types.h>
#include <linux/types.h>
#include <linux/bitops.h>
#define small_const_nbits(nbits) \
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
static inline void bitmap_zero(unsigned long *dst, int nbits)
{
if (small_const_nbits(nbits)) {
*dst = 0UL;
} else {
int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0, len);
}
}
#endif /* __LINUX_BITMAP_H */

View file

@ -158,4 +158,7 @@ struct ustat {
char f_fpack[6];
};
#define DECLARE_BITMAP(name, bits) \
unsigned long name[BITS_TO_LONGS(bits)]
#endif /* _LINUX_TYPES_H */

View file

@ -24,7 +24,7 @@
#include <common.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <usb/lin_gadget_compat.h>
#include <linux/bitmap.h>
/*
* USB function drivers should return USB_GADGET_DELAYED_STATUS if they

View file

@ -1,35 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* This is a Linux kernel compatibility layer for USB Gadget
*/
#ifndef __LIN_COMPAT_H__
#define __LIN_COMPAT_H__
#include <linux/bitops.h>
#include <linux/compat.h>
/* common */
#define DECLARE_BITMAP(name, bits) \
unsigned long name[BITS_TO_LONGS(bits)]
#define small_const_nbits(nbits) \
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
static inline void bitmap_zero(unsigned long *dst, int nbits)
{
if (small_const_nbits(nbits))
*dst = 0UL;
else {
int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
memset(dst, 0, len);
}
}
#define dma_cache_maint(addr, size, mode) cache_flush()
void cache_flush(void);
#endif /* __LIN_COMPAT_H__ */