These symbols are used in later patches for as addresses for
clearing the BSS area in the relocated U-Boot image.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The '__got_start' and '__got_end' symbols are used
only in the linker script to compute the value of
the 'num_got_entries' symbol.
Remove the symbols and use the SIZEOF(.got) command
to get the size of the .got section.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Fix access to global_data which is broken since commits:
commit 035cbe99cd
Author: Simon Glass <sjg@chromium.org>
Date: Thu Dec 13 20:49:08 2012 +0000
mips: Move per_clk and dev_clk to arch_global_data
Move these field into arch_global_data and tidy up. The other
CONFIG_JZSOC fields are used by various architectures, so just remove
the #ifdef bracketing for these.
Signed-off-by: Simon Glass <sjg@chromium.org>
commit 582601da2f
Author: Simon Glass <sjg@chromium.org>
Date: Thu Dec 13 20:48:35 2012 +0000
arm: Move lastinc to arch_global_data
Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
commit 66ee692347
Author: Simon Glass <sjg@chromium.org>
Date: Thu Dec 13 20:48:34 2012 +0000
arm: Move tbl to arch_global_data
Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
These are stripped down for bringup, They'll be filled out later
to match-up with the kernel DT contents, and/or as devices are
brought up (mmc, usb, spi, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com>
These files are for code that runs on the CPU (A15) on T114 boards.
At this time, there is no A15-specific code here.
As T114-specific run-time code is added, it'll go here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add I/O addresses of SPI SLINK controllers 1-6
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add tegra30 SPI SLINK nodes to fdt.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
SBC1 is SPI controller 1 on tegra30
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c
Some T30 tables needed whitespace fixes due to checkpatch complaints.
Signed-off-by: Tom Warren <twarren@nvidia.com>
The libfdt.h file is the definition file for libfdt. It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).
Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
trivial:
fdt_support.c:89:64: warning: Using plain integer as NULL pointer
fdt_support.c:325:65: warning: Using plain integer as NULL pointer
fdt_support.c:352:65: warning: Using plain integer as NULL pointer
For the following bad constant expression, We hardcode the max. number of
memory banks to four for the foreseeable future, and add an error with
instructions on what to do once it's exceeded:
fdt_support.c:397:22: error: bad constant expression
For the rest below, sparse found a couple of wrong endian conversions
in of_bus_default_translate() and fdt_get_base_address(), but
otherwise the rest is mostly annotation fixes:
fdt_support.c:64:24: warning: cast to restricted __be32
fdt_support.c:192:21: warning: incorrect type in assignment (different base types)
fdt_support.c:192:21: expected unsigned int [unsigned] [usertype] tmp
fdt_support.c:192:21: got restricted __be32 [usertype] <noident>
fdt_support.c:201:21: warning: incorrect type in assignment (different base types)
fdt_support.c:201:21: expected unsigned int [unsigned] [addressable] [usertype] tmp
fdt_support.c:201:21: got restricted __be32 [usertype] <noident>
fdt_support.c:304:13: warning: incorrect type in assignment (different base types)
fdt_support.c:304:13: expected unsigned int [unsigned] [usertype] val
fdt_support.c:304:13: got restricted __be32 [usertype] <noident>
fdt_support.c:333:13: warning: incorrect type in assignment (different base types)
fdt_support.c:333:13: expected unsigned int [unsigned] [usertype] val
fdt_support.c:333:13: got restricted __be32 [usertype] <noident>
fdt_support.c:359:13: warning: incorrect type in assignment (different base types)
fdt_support.c:359:13: expected unsigned int [unsigned] [usertype] val
fdt_support.c:359:13: got restricted __be32 [usertype] <noident>
fdt_support.c:373:21: warning: cast to restricted __be32
fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:963:48: expected restricted __be32 const [usertype] *p
fdt_support.c:963:48: got unsigned int [usertype] *<noident>
fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types)
fdt_support.c:971:48: expected restricted __be32 const [usertype] *p
fdt_support.c:971:48: got unsigned int [usertype] *<noident>
fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types)
fdt_support.c:984:29: expected restricted __be32 const [usertype] *cell
fdt_support.c:984:29: got unsigned int [usertype] *addr
fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types)
fdt_support.c:996:32: expected restricted __be32 const [usertype] *cell
fdt_support.c:996:32: got unsigned int [usertype] *addr
fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1041:41: expected restricted __be32 const [usertype] *cell
fdt_support.c:1041:41: got unsigned int [usertype] *addr
fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1053:41: expected restricted __be32 const [usertype] *range
fdt_support.c:1053:41: got unsigned int const [usertype] *[assigned] ranges
fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1064:53: expected restricted __be32 const [usertype] *addr
fdt_support.c:1064:53: got unsigned int [usertype] *addr
fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1110:50: expected restricted __be32 const [usertype] *addr
fdt_support.c:1110:50: got unsigned int *<noident>
fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types)
fdt_support.c:1121:49: expected restricted __be32 const [usertype] *cell
fdt_support.c:1121:49: got unsigned int *<noident>
fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types)
fdt_support.c:1147:60: expected restricted __be32 const [usertype] *addr
fdt_support.c:1147:60: got unsigned int *<noident>
fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static?
fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types)
fdt_support.c: In function 'fdt_node_offset_by_compat_reg':
fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default]
See also linux kernel commit 0131d897 "of/address: use proper
endianess in get_flags".
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
and, if including libfdt.h which includes libfdt_env.h in
the correct order, don't include fdt.h before libfdt.h.
this is needed to get the fdt type definitions set from
the project environment before fdt.h uses them.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.
[Hebbar Gururaja <gururaja.hebbar@ti.com>]
- Resolve merge conflict while rebasing. File structure is
changed in the mainline. So re-arrange the code accordingly.
- Update commit message to reflect the DDR3 part number
Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: RV-4162-C7
I2C-EEPROM: CAT32WC32
NAND: MT29F4G08_VFPGA63
PMIC: TPS65910A3
LCD
Supported:
UART 1
MMC/SD
ETH 1
USB
I2C
SPI
Not yet supported:
NAND
RTC
LCD
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
[trini: Add #define CONFIG_PHY_ADDR 0 to config]
Signed-off-by: Tom Rini <trini@ti.com>
Move these field into arch_global_data and tidy up. The other
CONFIG_JZSOC fields are used by various architectures, so just remove
the #ifdef bracketing for these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move these fields into arch_global_data and tidy up. The bExtUart field
does not appear to be used, so punt it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move these fields into arch_global_data and tidy up. This is needed for
both ppc and m68k since they share the i2c driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
Referenced arch/blackfin/lib/muldi3.c and the linux kernel.
Resolves issue seen when building u-boot for HW_MUL=0;
PLATFORM_CPPFLAGS += -mxl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-multiply-high
which resulted in error while linking to libgcc.a without mul hw (bs / m);
libgcc.a(_muldi3.o): In function `__muldi3':
.... src/gcc-4.6.2/libgcc/libgcc2.c:550: undefined reference to `_GLOBAL_OFFSET_TABLE_'
This link failure would not occur if we used gcc instead of ld directly, as
gcc will correctly use the crt's to resolve this link.
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy
up. Leave pci_clk on its own since this should really depend only on
CONFIG_PCI and not any particular chip type.
Signed-off-by: Simon Glass <sjg@chromium.org>
PPC has several of these fields, selected by chip type, although only one
is ever compiled in.
Instead, use a single field. It would be nice if this could be selected
by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when
CONFIG_PCI is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this field into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add arch/x86/cpu/cpu.c changes after Graeme's comments]
Signed-off-by: Tom Rini <trini@ti.com>
We currently assume that the global data pointer is at the start of
struct global_data. We want to remove this restriction, and it is
easiest to do this in C.
Remove the asm code and add equivalent code in C.
This idea was proposed by Graeme Russ here:
http://patchwork.ozlabs.org/patch/199741/
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Apply Graeme Russ' comments
http://patchwork.ozlabs.org/patch/206305/ here, re-order]
Signed-off-by: Tom Rini <trini@ti.com>
Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Address tlb_size in this patch as well]
Signed-off-by: Tom Rini <trini@ti.com>
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.
As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.
This patch applies to all archs at once. I can split it if this is really
a pain.
Signed-off-by: Simon Glass <sjg@chromium.org>
No one expects to end up in a delayed environment if
CONFIG_DELAY_ENVIRONMENT isn't defined.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Allen Martin <amartin@nvidia.com>
The patch adds an unified linker script file which
can be used for all currently supported MIPS targets.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Stefan Roese <sr@denx.de>
The OUTPUT_FORMAT command in linker scripts
was always misused due to some endianess and
toolchain problems.
Use GCC flags to ensure proper output format,
and get rid of the OUTPUT_FORMAT commands in
the board specific u-boot.lds files.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.
The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.
This approach makes the code a bit simpler because
it needs two instructions only.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
The difference between the address of the original
and the relocated _GLOBAL_OFFSET_TABLE_ is always
the same as the relocation offset.
The relocation offset is already computed and it is
available in the 's1/t6' register. Use that to adjust
the relocated _G_O_T_ address, instead of calculating
the offset again from the _gp value.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
When CoreNet Fabric (CCF) internal resources are consumed by the cores,
inbound SRIO messaging traffic through RMan can put the device into a
deadlock condition.
This errata workaround forces internal resources to be reserved for
upstream transactions. This ensures resources exist on the device for
upstream transactions and removes the deadlock condition.
The Workaround is for the T4240 silicon rev 1.0.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
If property 'fsl,sec-era' is already present, it is updated.
This property is required so that applications can ascertain which
descriptor commands are supported on a particular CAAM version.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in
the board config file doesn't work and memory is always initialized
to the value 0xdeadbeef. Only use this default value if a board doesn't
define CONFIG_MEM_INIT_VALUE.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
e6500 implements MMUv2 and supports power-of-2 page sizes rather than
power-of-4. Add support for such pages.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch adds the ability for the FSL DDR interactive debugger to
automatically run the sequence of commands stored in the ddr_interactive
environment variable. Commands are separated using ';'.
ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add copy command which allows copying of DIMM/controller settings.
This saves tedious retyping of parameters for each identical DIMM
or controller.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This fix allows the name of the stage to be specifed after the
controler and DIMM is specified. Prior to this fix, if the
data stage name is not the first entry on the command line,
the operation is applied to all controller and DIMMs.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
