Commit graph

161 commits

Author SHA1 Message Date
Simon Glass
8f0278eab4 x86: Add coreboot timestamps
Add selected coreboot timestamps into bootstage to get a unified view of
the boot timings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
5397d8058c x86: Support adding coreboot timestanps to bootstage
Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
d0b6f247a1 x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
f9083bbe78 x86: Remove ISR timer
This is no longer used since we prefer the more accurate TSC timer, so
remove the dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:33:21 -07:00
Simon Glass
29756d4447 x86: Remove old broken timer implementation
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:33:21 -07:00
Simon Glass
e761ecdbb8 x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
7949703a95 x86: Rationalise kernel booting logic and bootstage
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:33:20 -07:00
Simon Glass
c78a62acdf x86: Implement panic output for coreboot
panic_puts() can be called in early boot to display a message. It might
help with early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2013-05-13 13:33:20 -07:00
Simon Glass
7282d834cd x86: Declare global_data pointer when it is used
Several files use the global_data pointer without declaring it. This works
because the declaration is currently a NOP. But still it is better to
fix this so that x86 lines up with other archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:20 -07:00
Simon Glass
fa790fa0a9 x86: Remove legacy board init code
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:33:20 -07:00
Simon Glass
20a8b41d50 x86: Remove unused portion of link script
Since we don't have real-mode code now, we can remove this chunk of the link
script.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:31:18 -07:00
Simon Glass
dfdedd9c2e x86: Remove unused bios/pci code
Graeme Russ pointed out that this code is no longer used. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-05-13 13:31:18 -07:00
Andreas Bießmann
d2eae43ba8 lib: consolidate hang()
Delete all occurrences of hang() and provide a generic function.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01 16:41:08 -04:00
Simon Glass
8b42dfc3b6 x86: Fix DRAM bank size init with generic board
The intention of the memory init code is that it should work the same with
CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init()
is called prior to relocation with generic board (matching other archs)
and after relocation without generic board.

Adjust the init sequence so that dram_init() is not called in the generic
board case, which seems like the easiest fix for now. Also ensure that
relocation addresses are still calculated.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-15 16:26:09 -07:00
Simon Glass
192868b061 x86: Move PCI init before SPI init
It is possible that our PCI bus will provide the SPI controller, so change
the init order to make this work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Tom Rini
0ce033d258 Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
2013-03-18 14:37:18 -04:00
Simon Glass
949747b17f x86: Enable generic board
This will be used exclusively on x86, so enable it for the whole
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:01 -04:00
Simon Glass
e424c15c1f x86: Enable generic board support
This enables generic board support so that x86 boards can define
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
86cfb6bdec x86: Use sections header to obtain link symbols
These are defined in asm-generic/sections.h, so remove them from
architecture-specific files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
1938f4a5b6 Introduce generic pre-relocation board_f.c
This file handles common pre-relocation init for boards which use
the generic framework.

It starts up the console, DRAM, performs relocation and then jumps
to post-relocation init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
2013-03-15 16:13:59 -04:00
Simon Glass
716cc8cc7f Change stub example to use asm-generic/sections.h
We can use the declarations of __bss_start and _end from this header
instead of declaring them locally.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Simon Glass
1865286466 Introduce generic link section.h symbol files
We create a separate header file for link symbols defined by the link
scripts. It is helpful to have these all in one place and try to
make them common across architectures. Since Linux already has a similar
file, we bring this in even though many of the symbols there are not
relevant to us.

Each architecture has its own asm/sections.h where symbols specifc to
that architecture can be added. For now everything except AVR32 just
includes the generic header.

One change is needed in arch/avr32/lib/board.c to make this conversion
work.

Reviewed-by: Tom Rini <trini@ti.com> (version 5)
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:13:58 -04:00
Albert ARIBAUD
ef123c5253 Refactor linker-generated arrays
Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
	arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
	arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
	arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
	board/ait/cam_enc_4xx/u-boot-spl.lds
	board/davinci/da8xxevm/u-boot-spl-da850evm.lds
	board/davinci/da8xxevm/u-boot-spl-hawk.lds
	board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-12 23:28:40 +01:00
Simon Glass
62f7970a5a x86: Add error checking to x86 relocation code
This does not actually change normal behaviour, but adds a check that
should detect corruption of relocation data (e.g. by using BSS data
prior to relocation).

Also add additional debugging output when enabled.

During this investigation, two situations have been seen:
1. calculate_relocation_address():
	uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;

turns into
     111166f:	b8 83 c4 17 01       	mov    $0x117c483,%eax

whih is beyond the end of bss:

0117b484 g       .bss	00000000 __bss_end

Somehow the __bss_end here is 255 bytes ahead.

2. do_elf_reloc_fixups():

	uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;

Here the __text_start is 0 in the file:

 1111d9f:	bb a0 e0 13 01       	mov    $0x113e0a0,%ebx
1111da4:	81 ef 00 00 00 00    	sub    $0x0,%edi

As it happens, both of these are in pre-relocation code.

For these reasons we silent check and ignore bad relocations.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:48 -08:00
Simon Glass
f697d528ca x86: Support relocation of FDT on start-up
With CONFIG_OF_CONTROL we may have an FDT in the BSS region. Relocate
it up with the rest of U-Boot to keep the rest of memory free.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:47 -08:00
Simon Glass
f82d15ead1 x86: Rearrange the output input to remove BSS
At present BSS data is including in the image, which wastes binary space.
Remove it by rearranging the sections so that BSS is last.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:40 -08:00
Simon Glass
4b491b8dde x86: Add an __end symbol to signal the end of the U-Boot binary
With this symbol we can easy append something (e.g. an FDT) to the U-Boot
binary and access it from within U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:38 -08:00
Simon Glass
bc2df1afb9 x86: Permit bootstage and timer data to be used prior to relocation
It is useful to be able to access the timer before U-Boot has relocated
so that we can fully support bootstage.

Add new global_data members to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:36 -08:00
Simon Glass
8937140957 x86: Add basic cache operations
At present most x86 cache operations are undefined. Add a basic
implementation for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:34 -08:00
Simon Glass
5e98947f9b x86: Add function to get top of usable ram
The memory layout calculations are done in calculate_relocation_address(),
and coreboot has its own version of this function. But in fact all we
really need is to set the top of usable RAM, and then the base version
will work as is.

So instead of allowing the whole calculate_relocation_address() function
to be replaced, create board_get_usable_ram_top() which can be used by
a board to specify the top of the area where U-Boot relocations to.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:56:46 -08:00
Simon Glass
96dfc0633a x86: Remove unused real mode code
This code is pretty old and we want to support only 32-bit systems now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14 20:19:03 -08:00
Simon Glass
588a13f742 x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTOR
Invert the polarity of this option to simplify the Makefile logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Gabe Black <gabeblack@chromium.org>
2013-02-14 20:18:58 -08:00
Simon Glass
1f3a581495 x86: Remove sc520 cpu
This x86 CPU variant is no longer required as the boards that use it have
been removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14 20:18:58 -08:00
Gerald Van Baren
58864ddc72 Clean up libfdt.h includes
The libfdt.h file is the definition file for libfdt.  It is unnecessary
to include other fdt header files (the necessary ones are pulled in
by libfdt.h).

Signed-off-by: Gerald Van Baren <gvb@unssw.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Stefan Roese <sr@denx.de>
2013-02-08 22:32:38 -05:00
Kim Phillips
12e06fe03f treewide: include libfdt_env.h before fdt.h
and, if including libfdt.h which includes libfdt_env.h in
the correct order, don't include fdt.h before libfdt.h.

this is needed to get the fdt type definitions set from
the project environment before fdt.h uses them.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Jerry Van Baren <gvb.uboot@gmail.com>
2013-02-07 20:38:55 -05:00
Simon Glass
43cff66e03 x86: Use generic global_data
Move x86 over to use generic global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-04 09:05:46 -05:00
Simon Glass
6cb49c13f6 x86: Remove reset_status, relocoff from global_data
These fields are not used on x86, so punt them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:40:31 -05:00
Simon Glass
5a35e6c48e x86: Move gd_addr into arch_global_data
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add arch/x86/cpu/cpu.c changes after Graeme's comments]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:39:42 -05:00
Simon Glass
0cecc3b679 x86: Set up the global data pointer in C instead of asm
We currently assume that the global data pointer is at the start of
struct global_data. We want to remove this restriction, and it is
easiest to do this in C.

Remove the asm code and add equivalent code in C.

This idea was proposed by Graeme Russ here:
   http://patchwork.ozlabs.org/patch/199741/

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Apply Graeme Russ' comments
http://patchwork.ozlabs.org/patch/206305/ here, re-order]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-01 15:36:53 -05:00
Simon Glass
df4aa625a2 x86: Remove gdt_addr from arch_global_data
Remove this unused field.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:35:15 -05:00
Simon Glass
5cb48582ac Add architecture-specific global data
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.

As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.

This patch applies to all archs at once. I can split it if this is really
a pain.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-02-01 15:07:49 -05:00
Simon Glass
058d59b08d x86: Build vga video code only if CONFIG_VIDEO_VGA is defined
When running from coreboot we don't want this code, so make it
optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Simon Glass
a94e9d70e3 x86: Remove video_init() prototype from u-boot-x86.h
This function is not intended to be exported from the video drivers, so
remove the prototype. This fixes an error:

cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
c94663170b x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
2b9d2252aa x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
1350f1cce1 x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.

This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.

Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
7c71034d3c x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.

Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
b83058cd23 x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
488b8b242b x86: Fix MTRR clear to detect which MTRR to use
Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Stefan Reinauer
300081aa68 x86: Emit port 80 post codes in show_boot_progress()
This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00