Duncan Laurie 488b8b242b x86: Fix MTRR clear to detect which MTRR to use ... Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>		2012-12-06 14:30:43 -08:00
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cpu	x86: Fix MTRR clear to detect which MTRR to use	2012-12-06 14:30:43 -08:00
dts	x86: fdt: Create basic .dtsi file for coreboot	2012-12-06 14:30:42 -08:00
include/asm	x86: Add back cold- and warm-boot flags	2012-12-06 14:30:42 -08:00
lib	x86: Add support for CONFIG_OF_CONTROL	2012-12-06 14:30:42 -08:00
config.mk	x86: Wrap small helper functions from libgcc to avoid an ABI mismatch	2011-11-29 21:31:24 +11:00