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71290 commits

Author SHA1 Message Date
Marek Vasut
58cbf2eff5 ARM: imx: Revert "dh_imx6: Switch to full DM-aware"
This reverts commit 03a673cf49 ("dh_imx6: Switch to full DM-aware").
According to discussion [1], the patch is known to break the dh_imx6
board, however it made it upstream just before 2021.01-rc4, likely by
mistake. Revert this patch to put the board back into working order.

Also note that this board has no DM SPL support due to OCRAM size
limitations, but that is fine, as SPL DM support is optional.

[1] https://lists.denx.de/pipermail/u-boot/2020-June/417986.html

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ludwig Zenz <lzenz@dh-electronics.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>
2021-02-27 16:56:05 +01:00
Tom Rini
08cca188c1 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb
- fastboot updates / fixes
2021-02-26 15:11:08 -05:00
Tom Rini
b839fc9d47 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- new GigaDevice flash ids
- fixes for imx, nxp_spi drivers
2021-02-26 12:41:19 -05:00
Tom Rini
a3c6d287ba - Add USB host boot support in stm32mp1 config
- Enable uefi related commands for STMicroelectronics STM32MP15 boards
 - Remove duplicate uart nodes in stm32mp15 device tree
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Merge tag 'u-boot-stm32-20210226' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Add USB host boot support in stm32mp1 config
- Enable uefi related commands for STMicroelectronics STM32MP15 boards
- Remove duplicate uart nodes in stm32mp15 device tree
2021-02-26 12:41:06 -05:00
Ilias Apalodimas
1b3db349c0 configs: stm32mp1: enable uefi related commands
The board can boot with UEFI. With the latest changes in U-Boot's
EFI subsystem we also have support for EFI runtime variables, without
SetVariable support.  We can also store the EFI variables in a file on the
ESP partition and preserve them across reboots.
The env and efidebug commands are missing in order to configure
EFI variables and the efibootmgr though.  Since U-Boot's default config
enables other EFI related commands (e.g bootefi), let's add the env related
and efidebug commands and allow users to do that

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-26 15:45:22 +01:00
Patrick Delaunay
1a1a47cdba arm: dts: stm32mp15: remove duplicate uart nodes
Remove duplicated uart nodes introduced with commit 62f95af92a
("ARM: dts: stm32mp1: DT alignment with Linux kernel v5.9-rc4"),
because the uart nodes wasn't correctly ordered in alphabetic order.

Only cosmetic: the generated device tree don't change.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-26 15:44:58 +01:00
Marek Vasut
0bbfae717f ARM: stm32: Add USB host boot support
Add support for booting from USB pen drive, since USB host port is
available on the STM32MP1.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-26 15:39:12 +01:00
Patrice Chotard
0a7e5e5f10 usb: gadget: dwc2_udc_otg: Fix dwc2_gadget_start() and usb_gadget_register_driver()
Since commit 8745b9ebcc ("usb: gadget: add super speed support")
ums was no more functional on platform which use dwc2_udc_otg driver.

This was due to a too restrictive test which checked that the gadget
driver speed was either FS or HS.

So all gadget driver with max speed set to speed higher than
HS (SS in case of composite gadget driver in our case) are not
allowed, which is wrong.

Update the speed test in usb_gadget_register_driver() and in
dwc2_gadget_start() to allow all gadget driver speed equal or higher
than FS.

Tested on stm32mp157c-ev1 board.

Fixes: c791c8431c ("usb: dwc2: convert driver to DM_USB_GADGET")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-02-26 15:30:55 +01:00
Stefan Brüns
ba0b984bb0 usb: kbd: Also accept keyboards with Interrupt OUT endpoint
The OUT endpoint can just be ignored as it is not used, just as the
corresponding Set_Report request for IN-only interfaces. E.g. the
Linux gadget hid keyboard also provides an interrupt endpoint.

Also cleanup confusing debug messages like "found set protocol", which
is printed when a keyboard device is found, while the Set_Protocol request
is issued quite some time later.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2021-02-26 15:30:55 +01:00
Heiko Schocher
bc820d5bcc fastboot: add UUU command UCmd and ACmd support
add support for the UUU commands ACmd and UCmd.

Enable them through the Kconfig option
CONFIG_FASTBOOT_UUU_SUPPORT

base was commit in NXP kernel
9b149c2a2882: ("MLK-18591-3 android: Add FSL android fastboot support")

and ported it to current mainline. Tested this patch
on imx6ul based board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-02-26 15:30:55 +01:00
Sean Anderson
403c2e46b4 doc: Document partition specifications
This documents the way U-Boot understands partitions specifications.
This also updates the fastboot documentation for the changes in the
previous commit.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
1500c79dc3 doc: Rename k210 partitions anchor
This anchor is only for the k210 partition layout, so rename it
appropriately. This keeps it from conflicting with the (to be added)
anchor for U-Boot partitions in general.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
de1728ce4c fastboot: Allow u-boot-style partitions
This adds support for partitions of the form "dev.hwpart:part" and
"dev#partname". This allows one to flash to eMMC boot partitions without
having to use CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT. It also allows one to
flash to an entire device without needing CONFIG_FASTBOOT_MMC_USER_NAME.
Lastly, one can also flash MMC devices other than
CONFIG_FASTBOOT_FLASH_MMC_DEV.

Because devices can be specified explicitly, CONFIG_FASTBOOT_FLASH_MMC_DEV
is used only when necessary for existing functionality. For those cases,
fastboot_mmc_get_dev has been added as a helper function. This allows

There should be no conflicts with the existing system, but just in case, I
have ordered detection of these names after all existing names.

The fastboot_mmc_part test has been updated for these new names.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
ae5e6b4e8f fastboot: Move part_get_info_by_name_or_alias after raw_part_get_info_by_name
This makes the next commit more readable by doing the move now.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
f3cf964f2d fastboot: Remove mmcpart argument from raw_part_get_info_by_name
The only thing mmcpart was used for was to pass to blk_dselect_hwpart.
This calls blk_dselect_hwpart directly from raw_part_get_info_by_name. The
error handling is dropped, but it is reintroduced in the next commit
(albeit less specificly).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
81c1aa89e1 part: Support string block devices in part_get_info_by_dev_and_name
This adds support for things like "#partname" and "0.1#partname". The block
device parsing is done like in blk_get_device_part_str.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
9f7bb2825b part: Support getting whole disk from part_get_info_by_dev_and_name_or_num
This adds an option to part_get_info_by_dev_and_name_or_num to allow
callers to specify whether whole-disk partitions are fine.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
59715754e1 part: Give several functions more useful return values
Several functions in disk/part.c just return -1 on error. This makes them
return different errnos for different failures. This helps callers
differentiate between failures, even if they cannot read stdout.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
d4f22cb39e test: dm: Add test for fastboot mmc partition naming
This test verifies the mapping between fastboot partitions and partitions
as understood by U-Boot. It also tests the creation of GPT partitions,
though that is not the primary goal.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Sean Anderson
3f6fb77175 mmc: sandbox: Add support for writing
This adds support writing to the sandbox mmc backed by an in-memory
buffer. The unit test has been updated to test reading, writing, and
erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF
then that can be easily changed.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-26 15:30:55 +01:00
Tom Rini
99bebbd5b2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- turris_mox: Enhancements, mostlly defconfig changes (Pali)
- pci-aardvark: Set Max Payload Size and Max Read Request Size
                to 512 bytes (Pali)
- pci_mvebu: Minor cleanup and refactoring (Marek)
- Upgrade A38x DDR3 training to version 14.0.0 (Marek)
2021-02-26 07:55:16 -05:00
Tom Rini
d9bc92f554 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung 2021-02-26 07:54:27 -05:00
Tom Rini
94218ca9a8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv 2021-02-26 07:53:04 -05:00
Reto Schneider
783a15b351 mtd: nand: spi: Support GigaDevice GD5F1GQ5UExxG
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.

As the overlaps are huge, variable names have been generalized
accordingly.

Apart form the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.

New hardware features are not supported, namely:
 - Power on reset
 - Unique ID
 - Double transfer rate (DTR)
 - Parameter page
 - Random data quad IO

The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.

The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.

Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 16:01:37 +05:30
Hauke Mehrtens
12926f46fd mtd: nand: spi: Only one dummy byte in QUADIO
The datasheet only lists one dummy byte in the 0xEB operation for the
following chips:
* GD5F1GQ4xExxG
* GD5F1GQ4xFxxG
* GD5F1GQ4UAYIG
* GD5F4GQ4UAYIG

Reto Schneider:
- Linux patch ported to U-Boot
- Checked for compatibility with GD5F1GQ4xBxxG
- Fixed operation code in original commit message (0xEH -> 0xEB)

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 16:01:29 +05:30
Sean Anderson
a95d878ade mtd: spi-nor-core: Fix typo in documentation
This line should come before the docs for the next function.

Fixes: 7aeedac015 ("mtd: spi: Port SPI NOR framework from Linux")

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:48:42 +05:30
Sean Anderson
9bc772812d cmd: sf: Print error on test failure
The sf test command is used to test spi flashes (and spi masters). Printing
the exact error code is very helpful to those debugging the spi stack.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:48:00 +05:30
Sean Anderson
1bb8ca3b4b cmd: sf: Display errno on erase failure
If there is an error while erasing SPI flash, no errno is displayed. This
makes it difficult to determine the cause of the error. This change mirrors
the logic for write errors above.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:47:07 +05:30
Adam Ford
90d76f812b spi: nxp_fspi: Fix error reporting
On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the
rate the clock was able to set.  When checking for errors, it only
checks that it is not NULL.  Since positive numbers are not errors,
only check for negative numbers when handling errors.

Fixes: 383fded70c ("spi: nxp_fspi: new driver for the FlexSPI controller")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-02-26 15:09:38 +05:30
Marek Behún
2f0c18b158 ddr: marvell: a38x: fix comment in conditional macro
The code was processed with unifdef utility to omit portions not
relevant to A38x and DDR3. This removes usage of many macros, including
A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove
the macros from #else comment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
b1b17f8967 ddr: marvell: a38x: bump version to 14.0.0
Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the
version in the mv-ddr-devel branch of upstream repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.

There is a new version numbering system, where after 18.12.0 came
1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
heaterC
420e106ef1 ddr: marvell: a38x: enum mv_ddr_twin_die: change order
commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream.

@pali suggested this change
In commit 6285efb ("mv_ddr: add support for twin-die combined memory
device") was added support for twin-die combined memory device and
default value for explicitly uninitialized structure members is zero, s
also twin_die_combined is initialized to zero. Which means COMBINED
value.
As prior this commit there was no support for twin-die combined memory
device, default value for twin_die_combined should be NOT_COMBINED. This
change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED
has value zero.

Signed-off-by: heaterC <airyguy@gmx.de>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
a267943fd9 ddr: marvell: a38x: import code change from upstream
commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes code in ddr3_training.c.

Import this change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
2ab7bbf71e ddr: marvell: a38x: fix memory cs size function
commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream.

The funtion returnd cs size in byte instead of MB, that cause
calculation error since the caller was expected to get u32 and when he
got above 4G it refers it as 0.
The fix was to get the cs memory size from function as in MB and then
multiply it by 1MB.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
b85c6fb065 ddr: marvell: a38x: import header change from upstream
commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
44aeb28c9b ddr: marvell: a38x: disable WL phase correction stage in case of bus_width=16bit
commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream.

WL phase correcion stage is failing while using bus_width of 16bit, not
to be fix this stage is un-necessary when working with bus_width of 16
bit.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
32e7a6baef ddr: marvell: a38x: add support for twin-die combined memory device
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream.

the twin-die combined memory device should be treatened as X8
device and not as X16 one

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
[ - the default value for twin_die_combined is set to NOT_COMBINED for
    all boards, as this was default behaviour prior this change ]
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
52dd9b96fc ddr: marvell: a38x: add 16Gbit memory devices support
commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Baruch Siach
369e532691 ddr: marvell: a38x: allow board specific ODT configuration
commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
6e0532401b ddr: marvell: a38x: import header change from upstream
commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
9c4e06af0b ddr: marvell: a38x: fix memory size calculation using 32bit bus width
commit ab9240402a70cc02496683971779e75eff410ab4 upstream.

- function mv_ddr_spd_die_capacity_user_get() has a bug,
  since it insert a user memory enum to it,
  instead of SPD memory enum (which are different)
- fix: remove mv_ddr_spd_die_capacity_user_get() function.
- memory size with 64 and 32 bit already calculated correctly
  at mv_ddr_mem_sz_per_cs_get() function

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Stefan Chulski <Stefan.Chulski@cavium.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
6373a92d42 ddr: marvell: a38x: fix 32bit
commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream.

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
4d676739b9 ddr: marvell: a38x: import header change from upstream
commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header mv_ddr_topology.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Alex Leibovich
1dbd0bd599 ddr: marvell: a38x: add ddr 32bit ECC support
commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Alex Leibovich
5d88723ca4 ddr: marvell: a38x: add ddr32 support
commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream.

Required changes made for 32bit ddr support.
An update is made to the topology map, according to
bus_act_mask, set in the dram_port.c

Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
ab7dda724f ddr: marvell: a38x: import header change from upstream
commit a165037ec26f301be75e1fabc263643683e85255 upstream.

The commit mentioned above changes non-DDR3 stuff in upstream, but it
also changes header ddr_topology_def.h.

Import this header change to remain consistent with upstream.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Moti Buskila
69f084f5c6 ddr: marvell: a38x: fix write leveling suplementary algo
commit ce62bef8fac559e27245259882e45f19cdc293ad upstream.

- fix JIRA A7K8K-5056
- remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage
- the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory
  then the algorithm will fail, since it think that there are no phase to correct

Signed-off-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2021-02-26 10:22:29 +01:00
Marek Behún
2ca5b190c3 ARM: dts: armada-385-turris-omnia: rename node in -u-boot.dtsi file
The SPI NOR flash node name in main device tree for Turris Omnia is
called `spi-nor@0`.

Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0
so that U-Boot does not try to probe the same SPI NOR device multiple
times.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2021-02-26 10:22:29 +01:00
Marek Behún
5ddfd3f441 pci: pci_mvebu: set local dev to number 1
Linux displays the real PCIe card connected to a mvebu PCIe slot as
device 0, not 1. This is done by setting local dev number to 1, so that
the local "Marvell Memory controller" device is on address 1.

Let's do it also in U-Boot.

With this commit the pci command in U-Boot prints something like:
  => pci
  Scanning PCI devices on bus 0
  BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
  _____________________________________________________________
  00.00.00   0x168c     0x003c     Network controller      0x80

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00
Marek Behún
10eb2cc344 pci: pci_mvebu: refactor validation of addresses for config access
Refactor validation of bdf parameter in mvebu_pcie_read/write_config
functions.

We can simplify the code by putting the validation into separate
function.

Also there are always only two devices visible on local bus:
* on slot configured by function mvebu_pcie_set_local_dev_nr()
  (by default this register is set to 0) there is a
  "Marvell Memory controller", which isn't useful in root complex
  mode,
* on all other slots the real PCIe card connected to the PCIe slot.

We can simplify the code even more by simply allowing access only to
the real PCIe card.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-02-26 10:22:29 +01:00