Commit graph

367 commits

Author SHA1 Message Date
Dirk Eibach
60083261a1 arm: mvebu: Add gdsys ControlCenter-Compact board
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.

It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.

On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7 FPGA connected via PCIe
- mSATA
- USB3 host
- Atmel TPM

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 15:48:28 +01:00
Stefan Roese
2399e40120 arm: mvebu: AXP: Add possiblity to configure PEX detection pulse width
Tests have shown that on some boards the default width of the
configuration pulse for the PEX link detection might lead to
non-established PCIe links (link down). Especially under certain
conditions (higher temperature) and with specific PCIe devices
(in the case on the theadorable board its a Atheros PCIe WLAN
device). To enable a board-specific detection pulse width this weak
array "serdes_pex_pulse_width[4]" is introduced which can be
overwritten if needed by a board-specific version. If the board
code does not provide a non-weak version of this variable, the
default value will be used. So nothing is changed from the
current setup on the supported board.

Many thanks to Adam from Marvell for all his insights here and
his suggestion about testing with a changed detection pulse width.

Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Adam Shobash <adams@marvell.com>
Cc: Adam Shobash <adams@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 10:52:28 +01:00
Konstantin Porotchkin
c5330ae8c8 arm64: mvebu: Rename the db-88f3720 to armada-37xx platform
Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-23 08:50:50 +01:00
Mario Six
a1b6b0a9c1 arm: mvebu: Implement secure boot
The patch implements secure booting for the mvebu architecture.

This includes:
- The addition of secure headers and all needed signatures and keys in
  mkimage
- Commands capable of writing the board's efuses to both write the
  needed cryptographic data and enable the secure booting mechanism
- The creation of convenience text files containing the necessary
  commands to write the efuses

The KAK and CSK keys are expected to reside in the files kwb_kak.key and
kwb_csk.key (OpenSSL 2048 bit private keys) in the top-level directory.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:04:18 +01:00
Reinhard Pfau
3add68c996 arm: mvebu: spl.c: Remove useless gd declaration
ddaa905 ("arm: mvebu: Add DM (driver model) support") removed the
assignment of the gd pointer, but kept the (now superfluous) declaration
of the gd pointer.

Remove this declaration.

Signed-off-by: Reinhard Pfau <pfau@gdsys.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:02:49 +01:00
Mario Six
2ad4309441 mvebu: Add board_pex_config()
Allow boards to do some initialization when PCIe comes up.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:02:14 +01:00
Dirk Eibach
882d3fa6dd pci: mvebu: Fix Armada 38x support
Armada 38x has four PCI ports, not three.

The optimization in pci_init_board() seems to assume that every port has
three lanes. This is obviously wrong, and breaks support for Armada 38x.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2017-02-01 09:01:19 +01:00
Simon Glass
4585601ae2 Convert CONFIG_ARCH_MISC_INIT to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_MISC_INIT

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 17:38:41 -05:00
Simon Glass
a5d67547dd Convert CONFIG_BOARD_EARLY_INIT_F to Kconfig
This converts the following to Kconfig:
   CONFIG_BOARD_EARLY_INIT_F

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-01-25 17:38:32 -05:00
Tom Rini
e5ec48152a Kconfig: Migrate BOARD_LATE_INIT to a select
This option should not really be user selectable.  Note that on PowerPC
we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
conditional on that.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
2017-01-24 10:35:54 -05:00
Masahiro Yamada
45a68fe267 mmc: move some SDHCI related options to Kconfig
While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.

This commit was created in the following steps.

[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g
s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g
s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g
s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g
s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g
s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g
'

[2] create the Kconfig entries in drivers/mmc/Kconfig

[3] Move the options by the following command
tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \
MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR

[4] Sort drivers/mmc/Makefile for readability

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-12-29 13:08:16 -05:00
Konstantin Porotchkin
0d92f2141a arm64: mvebu: Fix A8K memory mapping and add documentation
Fix the MMU mapping for A8K device family:
 - Separate A7K and A8K memory mappings
 - Fix memory regions by including IO mapping for all
   3 PCIe interfaces existing on each connected CP110 controller
Add A8K memory mapping documentation with all regions
configured by Marvell ATF.

Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-21 09:52:35 +01:00
Konstantin Porotchkin
b58385df3a arm64: mvebu: Add L3 cache flush functionality to A8K family
Add missing L3 cache flush functionality which absence prevents
Linux kernel from normal boot in case the L3 cache is enabled
by ATF.
The L3 cache is named the "last level" cache in order to keep
the terminology similar to the ATF code.
This cache should not be disabled by u-boot since the Linux
kernel cannot activate it, so it is activates at ATF stage.
However the cache flush is required for preventing data corruption
after disabling the MMU and the data cache before passing control
to the loaded Linux image.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-12 09:05:28 +01:00
Stefan Roese
059f75d501 arm64: mvebu: Restrict memory size to a usable maximum
Not all memory is mapped in the MMU. So we need to restrict the memory
size so that U-Boot does not try to access it. Also, the internal
registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB
are mapped for system memory. This is what we pass to the U-Boot
subsystem here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-05 13:34:33 +01:00
Stefan Roese
6324fdc547 arm64: mvebu: Add regions for PCI spaces to the memory map
To use the PCIe driver, its controller memory and the PCIe regions need
to get mapped in the MMU. Otherwise these areas can't be accessed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-05 13:34:33 +01:00
Stefan Roese
d7dd358f93 arm64: mvebu: Init COMPHY from the slave-CP on the A8k
The Armada8k implements 2 CPs (communication processors) and the 2nd
CP also is equipped with a COMPHY controller. This patch now loops
over all enabled MISC devices (CP110) enabled in the DT to initialize
all CPs.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-05 13:28:23 +01:00
Stefan Roese
3fef31a392 arm64: mvebu: Add slave CP area to the memory map
To enable access to the slave CP its memory needs to be added to the
MMU memory map.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-05 13:28:23 +01:00
Stefan Roese
633fa0e710 arm64: mvebu: Rename db-88f7040 files to armada-8k
This moves some of the Armada DB-88F7040 board specific files to a more
generic name: armada-8k. This is in preparation for the Armada-8k
support which will be added soon. And since both platforms share
most devices, lets also share most source files to not duplicate
the code here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-12-05 13:28:23 +01:00
Chris Packham
a53d97ae85 arm: mvebu: move SYS_MVEBU_PLL_CLOCK to Kconfig
The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375,
38x and 39x.

[ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ]

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-12-01 09:09:20 +01:00
Stefan Roese
6f8c2d4906 arm64: mvebu: Add Armada 7K db-88f7040 development board support
This patch adds basic support for the Marvell Armada 7K DB-88F7040
development board. Supported are the following interfaces:
- UART
- SPI (incl. SPI NOR)
- I2C
- USB
- SATA / AHCI

Support for other interfaces will follow.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-09-27 17:29:54 +02:00
Stefan Roese
21b29fc64e arm64: mvebu: Add basic support for the Marvell Armada 7K/8K SoC
Compared to the Armada 3700, the Armada 7K and 8K are much more on the
high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as
opposed to the Cortex-A53 for the Armada 3700.

The Armada 7K and 8K also use a fairly unique architecture, internally
they are composed of several components:

- One AP (Application Processor), which contains the processor itself
  and a few core hardware blocks. The AP used in the Armada 7K and 8K
  is called AP806, and is available in two configurations:
  dual Cortex-A72 and quad Cortex-A72.
- One or two CP (Communication Processor), which contain most of the I/O
  interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one
  CP, while the 8K family chips integrate two CPs, providing two times
  the number of I/O interfaces available in the CP.
  The CP used in the 7K and 8K is called CP110.

All in all, this gives the following combinations:

- Armada 7020, which is a dual Cortex-A72 with one CP
- Armada 7040, which is a quad Cortex-A72 with one CP
- Armada 8020, which is a dual Cortex-A72 with two CPs
- Armada 8040, which is a quad Cortex-A72 with two CPs

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support,
starting with the Marvell DB-88F7040 development board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-09-27 17:29:54 +02:00
Stefan Roese
01e62c7f11 arm64: mvebu: Add Armada 3700 db-88f3720 development board support
This patch adds basic support for the Marvell Armada 3700 DB-88F3720
development board. Supported are the following interfaces:
- UART
- SPI (incl. SPI NOR)
- I2C
- Ethernet

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
2016-09-27 17:29:53 +02:00
Stefan Roese
f61aefc150 arm64: mvebu: Add support for the Marvell Armada 3700 SoC
The Armada 3700 integrates the following interfaces (not complete list):
- Dual Cortex-A53 ARMv8
- USB 3.0
- SATA 3.0
- PCIe 2.0
- 2 x Gigabit Ethernet 1Gbps / 2.5Gbps
- ...

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support
for the Marvell DB-88F3720 development board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
2016-09-27 17:29:53 +02:00
Chris Packham
c0def248ca arm: mvebu: add DB-88F6820-AMC board
This board is a plug in card for Marvell's switch system development
kits. Form-factor aside it is similar to the DB-88F6820-GP with the
following differences.
- TCLK is 200MHz
- SPI1 is used
- No SATA
- No MMC
- NAND flash

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-24 10:07:48 +02:00
Chris Packham
53d601fdcd arm: mvebu: create generic 88F6820 config option
88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP
board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which
selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards
using the 88F6820 can be added.

Stefan:
Change 88F6820 for clearfog as well.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-24 10:07:48 +02:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Tom Rini
067716bac5 ARM: Move SYS_CACHELINE_SIZE over to Kconfig
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
2016-08-26 17:04:46 -04:00
Chris Packham
c90d7ab6b0 arm: mvebu: a38x: typo fix cpabilities -> capbilities
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-08-26 08:33:52 +02:00
Chris Packham
014a357bba arm: mvebu: a38x: update serdes error handling
Ensure appropriate error messages are generated. Previously all errors
indicated that the serdes was already in use. Now appropriate error
messages are given.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-08-26 08:33:44 +02:00
Chris Packham
d7b4731efd arm: mvebu: Add support for NAND interface on A-38x
The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-08-26 08:33:21 +02:00
Marek Vasut
2b1cdafa9f common: Pass the boot device into spl_boot_mode()
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.

The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-26 20:17:22 +02:00
Tom Rini
89cb2b5f8b configs: Re-sync with cmd/Kconfig
Update the config.h and defconfig files for the commands that 8e3c036
converted over to Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-25 15:09:47 -04:00
Stefan Roese
d9cb860d30 arm: mvebu: Add base address for 2nd I2C controller
Add MVEBU_TWSI1_BASE define so that the 2nd I2C controller on e.g. AXP
can be used.

Signed-off-by: Stefan Roese <sr@denx.de>
2016-04-12 11:13:40 +02:00
Stefan Roese
ebe7890321 arm: mvebu: Don't enable d-cache on A375
Armada 375 still has some problems with d-cache enabled in the ethernet
driver (mvpp2). So lets keep the d-cache disabled until this is solved.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-04-04 11:22:15 +02:00
Stefan Roese
606576d54b arm: mvebu: Add basic support for Armada 375 eval board db-88f6720
This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1

Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-04-04 11:22:10 +02:00
Stefan Roese
09e89ab4af arm: mvebu: Add basic support for the Marvell Armada 375 SoC
This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-04-04 11:22:05 +02:00
Stefan Roese
21324ddb8b arm: mvebu: Add some SPI CS attributes
These attribute defines may be used to map an area of memory for direct
access to the specific SPI devices. See SPI Direct Access Mode for
further information.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:47:56 +01:00
Stefan Roese
b20c38a973 arm: mvebu: Add support for the Armada XP theadorable board
This patch adds support for the Armada XP (MV78260) based theadorable
board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
LCD and SATA (SSD) interfaces / devices.

Two defconfigs are added:

theadorable_defconfig:
The production U-Boot version with a stripped down drivers and feature
list. This removes networking, USB and PCI support.

theadorable_debug_defconfig:
The debugging / testing U-Boot version with full support for all drivers.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-01-27 07:45:43 +01:00
Stefan Roese
913d1be208 video: Add support for Armada XP LCD controller
This patch adds basic support for the LCD controller of the Marvell
Armada XP SoC.

An AXP based custom board port will be added later, to use this
driver to display a splash screen via the bmp command later.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
[agust: rebased]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2016-01-23 22:58:07 +01:00
Phil Sutter
aefb8f4c32 mvebu: Support Synology DS414
This adds support for the MV78230 based DS414 NAS by Synology. The
relevant bits have been extracted from the 'synogpl-5004-armadaxp'
package Synology kindly published, garnished with a fair amount of
trial-and-error.

Sadly, support is far from perfect. The major parts I have failed in
are SATA and XHCI support. Details about these and some other things
follow:

Device Tree
-----------

The device tree file armada-xp-synology-ds414.dts has been copied from
Linux and enhanced by recent U-Boot specific changes to
armada-xp-gp.dts.

SATA Support
------------

There is a Marvell 88SX7042 controller attached to PCIe which is
supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv.
I'm not sure if extending the latter to support PCI devices is worth the
effort at all. Porting sata_mv from Linux exceeded my brain's
capacities. :(

XHCI Support
------------

There is an EtronTech EJ168A XHCI controller attached to PCIe which
drives the two rear USB3 ports. After a bit of playing around I managed
to get it recognized by xhci-pci, but never was able to access any
devices attached to it. Enabling it in ds414 board config shows that it
does not respond to commands for whatever reason. The (somewhat) bright
side to it is that it is not even supported in Synology's customized
U-Boot, but that also means nowhere to steal the relevant bits from.

EHCI Support
------------

This seems functional after issuing 'usb start'. At least it detects USB
storage devices, and IIRC reading from them was OK. OTOH Linux fails to
register the controller if 'usb start' wasn't given before in U-Boot.

According to Synology sources, this board seems to support USB device
(gadget?) mode. Though I didn't play around with it.

PCIe Support
------------

This is fine, but trying to gate the clocks of unused lanes will hang
PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI.

DDR3 Training
-------------

Marvell/Synology uses eight PUPs instead of four. Does not look like
this is meant to be customized in mainline U-Boot at all. OTOH I have
no idea what a "PUP" actually is.

PEX Init
--------

Synology uses different values than mainline U-Boot with this patch:
pex_max_unit_get returns 2, pex_max_if_get returns 7 and
max_serdes_lines is set to 7. Not changing this seems to not have an
impact, although I'm not entirely sure it does not cause issues I am not
aware of.

Static Environment
------------------

This allows to boot stock Synology firmware at least. In order to be a
little more flexible when it comes to booting custom kernels, do not
only load zImage partition, but also rd.gz into memory. This way it is
possible to use about 7MB for kernel with piggyback initramfs.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
6202953df4 mvebu: Add rudimental MV78230 support
This adds basic support for Marvell's MV78230 SoC which belongs to the
Armada XP series.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
4290252148 mvebu: Introduce kconfig symbols for SoC variants
This patch adds intermediate kconfig symbols which select their SoC
family. Boards then select them instead of the family symbol directly.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
beadff1731 mvebu: axp: refactor board_sat_r_get() and caller
Instead of calling board_sat_r_get() only for those boards providing the
satr11 value via I2C, call it for all boards and return static values
for those not using I2C.

In addition to that, make this a weak function to allow for board code
to override it.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
9a04527840 drivers/pci/pci_mvebu: Fix for boards with X4 lanes
Armada XP has support for X4 lanes, boards specify this in their
serdes_cfg. During PEX init in high_speed_env_lib.c, the configuration
is stored in GEN_PURP_RES_2_REG.

When enumerating PEX, subsequent interfaces of an X4 lane must be
skipped. Otherwise the enumeration hangs up the board.

The way this is implemented here is not exactly beautiful, but it mimics
how Marvell's BSP does it. Alternatively we could get the information
using board_serdes_cfg_get(), but that won't lead to clean code, either.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
f4db6c976c arm: mvebu: Add runtime detection of UART (xmodem) boot-mode
This patch adds runtime detection of the Marvell UART boot-mode (xmodem
protocol). If this boot-mode is detected, SPL will return to the
BootROM to continue the UART booting.

With this patch its now possible, to generate a U-Boot image that
can be booted either from the strapped boot-device (e.g. SPI NOR, MMC,
etc) or via the xmodem protocol from the UART. In the UART case,
the kwboot tool will dynamically insert the UART boot-device type
into the image. And also patch the load address in the header, so
that the mkimage header will be skipped (as its not expected by the
Marvell BootROM).

This simplifies the development for Armada XP / 38x based boards.
As no special images need to be generated by selecting the
MVEBU_BOOTROM_UARTBOOT Kconfig option.

Since the Kconfig option MVEBU_BOOTROM_UARTBOOT is not needed any
more, its now completely removed.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
a5f88877af arm: mvebu: Add runtime boot-device detection
This patch adds runtime boot-device detection to SPL U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
a9fc5a247c arm: mvebu: Make local structs static const
As these structs are local only and const, declare them accordingly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
d35831f6fe arm: mvebu: Move SAR register defines into header
This is preparation for the runtime bootmode detection in spl.c.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
81e33f4b65 arm: mvebu: Move SoC selection (A38X vs AXP) into Kconfig
Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.

Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.

And CONFIG_DDR3 is removed, as its not referenced anywhere.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
b322c83aa4 arm: mvebu: Consolidate board Kconfig options into one file
Merging all the board specific Kconfig options into the main Kconfig file
for mach-mvebu makes things easier to maintain.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
d718bf2c9e arm: mvebu: Print CPU and SDRAM frequency upon startup
With this patch, the CPU and the DDR frequencies will get printed in the
U-Boot startup messages. Resulting in such a log:

U-Boot 2016.01-rc2-00188-gb8eeaec-dirty (Dec 21 2015 - 12:32:35 +0100)

SoC:   MV78460-B0 at 1600 MHz
I2C:   ready
DRAM:  4 GiB (800 MHz, ECC not enabled)
...

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
e25d5a95e7 arm: mvebu: Make serdes setup on Armada XP less noisy
Change some of the PEX configuration output lines from always output to
only ouput upon specific debug enabling.

This changes the SPL output from:

U-Boot SPL 2016.01-rc2-00037-g9353a7f (Dec 10 2015 - 10:27:42)
High speed PHY - Version: 2.1.5 (COM-PHY-V20)
Update Device ID PEX0782611ab
Update Device ID PEX1782611ab
Update Device ID PEX2782611ab
Update Device ID PEX3782611ab
Update Device ID PEX8782611ab
Update PEX Device ID 0x78260
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.4
DDR3 Training Sequence - Ended Successfully

to:

U-Boot SPL 2016.01-rc2-00037-g9353a7f-dirty (Dec 10 2015 - 10:32:04)
High speed PHY - Version: 2.1.5 (COM-PHY-V20)
High speed PHY - Ended Successfully
DDR3 Training Sequence - Ver 5.7.4
DDR3 Training Sequence - Ended Successfully

Resulting in a little faster bootup time.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
84877c656c arm: mvebu: Don't include "netdev.h" in cpu.c
This is not needed any more since the switch to DM / DTS network
initialization on MVEBU. Lets remove it, as it otherwise leads
to compilation warning when CONFIG_NET is not enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
bf0db8b82a arm: mvebu: Add support for MV78260
This patch adds support for the dual core Armada XP variant, the
MV78260. It has some minor differences to the 4-core MV78460,
e.g. only 12 serdes lanes.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
2016-01-14 14:08:59 +01:00
Stefan Roese
00a457b22e arm: mvebu: Don't use 0 as board ID as its used for the custom boards
Using board ID 0 is reserved for the non-Marvell "custom" boards. So
move the board ID's to reflect this.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
2016-01-14 14:08:59 +01:00
Stefan Roese
ab8a4c6afa arm: mvebu: Simplify code in setup_usb_phys() a bit
Use the clrbits() / setbits() functions instead of clrsetbits() when
bit are only cleared or set.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
c86d53fd88 arm: mvebu: Don't disable cache at startup on Armada XP at all
This patch leaces the cache configuration untouched for the AXP in the
setup done by the BootROM. Resulting in the cache still being enabled
at the startup of U-Boot. This leads to a slightly faster boot to the
U-Boot prompt (or Linux of course).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
f4e6ec7dc6 arm: mvebu: Don't call arch_cpu_init() from SPL at all
This patch removes the call to arch_cpu_init() in the SPL U-Boot version.
As SPL does not need all the configuration done in this function. And
also does not need the reconfiguration of the internal register
address to 0xf1000000. This will be done by the main U-Boot later on.

This also fixes a problem with the timer not beeing initialized on AXP,
as needed for the mdelay in the setup_usb_phys(). This will now only
be called once in main U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
f0e8173a38 arm: mvebu: Add v7_outer_cache_disable function for AXP & A38x
Add functionality to correctly disable the L2 cache on the Armada XP
and 38x platforms.

Without this, booting into Linux on ClearFog (A38x) results in a hangup
without any output on the serial console at all. Even with earlyprintk
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
3e5ce7ceeb arm: mvebu: Enable L2 cache on Armada XP
Until now, the L2 cache was never enabled again in U-Boot. To get
even better performance (bootup time), lets enable the L2 cache
in U-Boot. This code was taken from the Linux kernel.

A performance gain was measured on the DB-MV784MP-GP board by testing
with tftpboot and sata commands.

This patch also cleans up the L2 cache related code. And makes sure that
the L2 cache is only disabled once.

Please note that A38x still runs with L2 cache disabled. And needs
to be enabled for this SoC in a separate patch if needed or desired.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
0299c90f39 arm: mvebu: Add SolidRun ClearFog Armada 38x initial support
This patch adds basic support for the SolidRun ClearFog Armada 38x based
board to mainline U-Boot. Supported interfaces / devices are:
- DDR3
- UART
- MMC
- Ethernet port 0 (connected to dedicated PHY)
- I2C

The included DT source was taken from Russell King's ftp server:
http://www.home.arm.linux.org.uk/~rmk/clearfog/

With only minor modifications, like the addition of some aliases and the
"u-boot,dm-pre-reloc" property.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Stefan Roese
8a02ec1dc6 arm: mvebu: Move some defines to common include file
This patch moves some config options to the mvebu common include file.
Making it easier to not forget these defines for new boards.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
2016-01-14 14:08:59 +01:00
Stefan Roese
e3b9c98a23 net: mvneta: Convert to driver model
Update this driver to support driver model. As all MVEBU boards using
this driver are converted with this patch, the non-driver-model code
can be removed completely. This is also the reason why this patch
is quite big and includes a) the driver change and b) the
platform change. As its not git-bisect save otherwise.

With this conversion, some parameters are now extracted from the
DT instread of using the config header defines. The supported
properties right now are:

PHY-mode ("phy-mode") and PHY-address ("reg").

The base addresses for the ethernet controllers can be removed from
the header files as well.

Please note that this patch also removes the E1000 network driver
from some MVEBU config headers. This is necessary, as with DM_ETH
configured and the e1000 driver enabled, the PCI driver also needs
to support DM. But the MVEBU PCI(e) driver still needs to get
ported to DM. When this is done, the E1000 driver can be enabled
again.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
2016-01-14 14:08:59 +01:00
Stefan Roese
09a54c009e arm: mvebu: Add SPI driver model support
This patch enables the DM support for the SPI driver and the
SPI NOR flash chips. Some MVEBU boards boot from SPI NOR, so
adding the aliases and enabling CONFIG_DM_SEQ_ALIAS is needed
here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Simon Glass <sjg@chromium.org>
2016-01-14 14:08:59 +01:00
Stefan Roese
6451223a8d arm: mvebu: Add DM and OF_CONTROL support to SPL
This patch adds full DM support to the SPL on MVEBU. Currently
only serial is supported. Other drivers will follow.

This patch also adds the necessary config values for the DEBUG UART
to the MVEBU defconfig files. This came in handy while implementing
this DM support.

Additionally, the mvebu specific SPL linker script is removed and
this common one is used instead:

   arch/arm/cpu/u-boot-spl.lds

This common linker script already handles all special cases. No need
to reinvent the wheel for MVEBU here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Simon Glass <sjg@chromium.org>
2016-01-14 14:08:59 +01:00
Stefan Roese
2fbc18fe21 arm: mvebu/kirkwood: Use common timer functions
By using the common timer functions for mvebu/kirkwood we can get rid of quite
a lot of code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
9eb14cc443 arm: mvebu: Configure ARP timeout and retry count
As some MVEBU platforms using the MVNETA driver seem to miss the
first ARP packet, lets reduce the timeout and increase the retry
count. This increases the speed for communication establishment.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-11-29 16:02:44 +01:00
Kevin Smith
490753ace3 arm: mvebu: a38x: serdes specification cleanup
Instead of allocating space in the driver for the serdes
specification table, just allow the board file to set a pointer
to it.  Also, allow the board to only specify the lanes that are
used instead of including unused lanes.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Kevin Smith
18c202aa54 arm: mvebu: a38x: Add const to some function calls
Functions that do not modify the pointer passed should declare it
as const.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Kevin Smith
544acb07ec arm: mvebu: a38x: Remove unsupported topologies
A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support.  Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM.  If this needs to be done, it should be
handled in the board file, not in core code.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Fabio Estevam
f8fdb81f6c compat: Remove is_power_of_2() definition
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 16:46:59 -05:00
Stefan Roese
9cffb2335c arm: mvebu: Add DM (driver model) support
This patch adds driver model support for some Marvell MVEBU SoC's. Including
Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now
selected automatically for MVEBU platforms.

With this DM support now available for MVEBU, hardcoding the base addresses
and other information is not necessary any more. Probing should be done
by using the values provided via the device tree now instead. For this
the driver also need to be converted to DM. Patches for some of the drivers
will follow.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:01 +02:00
Stefan Roese
78de2c0c3e arm: mvebu: Do not call board_init_r() from board_init_f()
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the MVEBU SPL with the correct SPL design as well as reduces
the stack utilisation slightly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:01 +02:00
Stefan Roese
42cc034f19 arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL
When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-10-21 02:25:00 +02:00
Stefan Roese
944c7a3176 arm: mvebu: Add option to use UART xmodem protocol via kwboot
This patch enables the use of the kwboot tool, to boot mainline U-Boot
on the Marvell Armada XP/38x SoC's. This is done by returning to the
SoC's BootROM after SPL has initialized the SDRAM. We need to make sure
to not reconfigure the internal register space and MBARs. Otherwise
the BootROM will not be able to continue after SPL jumps back to it.

To use this feature, please don't forget to change the BOOT_FROM line
in your board specfic kwbimage.cfg file this way:

    BOOT_FROM uart

Tested on these Marvell eval boards:
DB-MV784MP-GP - Armada XP
DB-88F6820-GP - Armada 38x

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-21 02:25:00 +02:00
Stefan Roese
c3d891405b arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig file
Introduce a mach-mvebu/Kconfig for all Armada based SoC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-10-20 07:12:44 +02:00
Stefan Roese
787ddb7cd1 arm: mvebu: timer.c: Explicitly move "init_done" var to data section
As reported by Simon Guinot, commit ade741b3
"arm: mvebu: Call timer_init early before PHY and DDR init" breaks
Kirkwood platforms. As the static variable "init_done" is not
available at that early boot time. This patch moves it to explicitly
to the data section, making it available at that time.

Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Simon Guinot <simon.guinot@sequanux.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
2015-10-01 02:00:02 +02:00
Stefan Roese
cefd764222 arm: mvebu: Fix internal register config on A38x
Currently booting on A38x is broken. As the current code tries to detect
the SoC family to disable the MMU for the A38x at runtime. But before the
internal registers are switched to the new location (0xf100.0000), this
runtime detection does not work. As all macros / defines are already
assigned to the new location at 0xf100.0000. But the registers are sill
mapped to the default location at 0xd000.0000.

This patch now makes sure, no such runtime detection is used before
the internal registers are configured to the new location. After this,
the remaining cache cleanup is executed.

Signed-off-by: Stefan Roese <sr@denx.de>
Reported-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-10-01 01:59:34 +02:00
Heiko Schocher
92a3188d7d bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11 17:15:32 -04:00
Anton Schubert
9c28d61c8e pci: mvebu: Add PCIe driver
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.

Besides the driver, this patch also removes the statically defined
PCI MBUS windows. As they are not needed anymore, since this PCIe
driver now creates the windows dynamically.

Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000
PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp
eval board using this Intel E1000 PCIe card in the PCIe 0 slot.

This port was done in cooperation with Anton Schubert.

Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-08-17 18:49:43 +02:00
Stefan Roese
0ceb2dae78 arm: mvebu: Add complete SDRAM ECC scrubbing
This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:

1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:33 +02:00
Stefan Roese
a8b57a90ec arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()
Rework these functions so that dram_init_banksize() does not call
dram_init() again. It only needs to set the banksize values in the
bdinfo struct.

Make sure to also clip the size of the last bank if it exceeds the
maximum allowed value of 3 GiB (0xc000.0000). Otherwise other
address windows (e.g. PCIe) will overlap with this memory window.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:29 +02:00
Stefan Roese
8a83c65f57 arm: mvebu: Display ECC enabled / disabled upon bootup
This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM
bootup text. Making it easier for board with SPD DIMM's to see,
if ECC is enabled or not.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:19 +02:00
Stefan Roese
dee40d26d3 arm: mvebu: Enable USB EHCI support on Armada XP
This patch enables the USB EHCI support for the Marvell Armada XP (AXP)
SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure
the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done
this already in the bin_hdr (SPL U-Boot). Without this, accessing the
controller registers in U-Boot or Linux will hang the CPU.

Additionally, the AXP uses a different USB EHCI base address. This
patch also takes care of this by runtime SoC detection in the Marvell
EHCI driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:07 +02:00
Stefan Roese
2a0b7dc3b6 arm: mvebu: Enable NAND controller on MVEBU SoC's
This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.

As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:02 +02:00
Stefan Roese
501c098a1f arm: mvebu: Disable MBUS error propagation
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:48:57 +02:00
Stefan Roese
2b181b5b04 arm: mvebu: Flush caches and disable MMU only on A38x
Only with disabled MMU its possible to switch the base register address
on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also
not accessible, as its still locked to cache.

So to fully release / unlock this area from cache, we need to first
flush all caches, then disable the MMU and disable the L2 cache.

On Armada XP this does not seem to be needed. Even worse, with this
code added, I sometimes see strange input charactes loss from the
console.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:48:52 +02:00
Stefan Roese
5b72dbfc23 arm: mvebu: Setup the MBUS bridge registers
With this patch, the MBUS bridge registers (base and size) are
configured upon each call to mbus_dt_setup_win(). This is needed, since
the board code can also call this function in later boot stages. As
done in the maxbcm board.

This is needed to fix a problem with the secondary CPU's not booting
in Linux on AXP.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:48:46 +02:00
Stefan Roese
8ed20d6501 arm: mvebu: Change MBUS base addresses and sizes
This patch changes the MBUS base addresses and sizes to use more
generic names and also adds defines for the sizes. It also moves
the base address to higher addresses.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:48:34 +02:00
Stefan Roese
8822fe1683 arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INIT
CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid
of all references here.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:41:33 +02:00
Stefan Roese
8ed43b966c arm: mvebu: Add SPL SDIO/MMC boot support
This patch adds basic SDIO/MMC booting support to MVEBU SoC's. Since
I don't know of a way to test the boot-device upon runtime, this patch
hardcodes the spl_boot_device instead.

Tested on Marvell DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-07-24 09:45:30 +02:00
Stefan Roese
ad6ac7aa00 arm: mvebu: a38x: Use correct PEX register access macros
Remove the incorrect PEX macros from the DDR header. And insert the
correct ones in ctrl_pex.h instead.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:39:25 +02:00
Stefan Roese
ff9112df8b arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.

This will be the new structure:

     drivers/ddr/marvell/axp
     Supporting Armada XP (AXP) devices (and perhaps Armada 370)

     drivers/ddr/marvell/a38x
     Supporting Armada 38x devices (and perhaps Armada 39x)

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:38:30 +02:00
Stefan Roese
edb4702533 arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdr
This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:38:14 +02:00
Stefan Roese
29b103c733 arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directory
With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:38:05 +02:00
Stefan Roese
9f62b44ec7 arm: mvebu: Disable MMU before changing register base address
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not
accessible, as its still locked to cache.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:37:36 +02:00
Stefan Roese
e3cccf9eb2 arm: mvebu: spl.c: Add call to board_early_init_f()
Pin muxing needs to be done before UART output, since on A38x the UART
pins need some re-muxing for output to work.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:37:20 +02:00
Stefan Roese
21427708a6 arm: mvebu: Use default reg base address for SPL on A38x
On A38x switching the regs base address without running from
SDRAM doesn't seem to work. So let the SPL still use the
default base address and switch to the new address in the
mail u-boot later.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:37:10 +02:00
Stefan Roese
ade741b389 arm: mvebu: Call timer_init early before PHY and DDR init
Without calling timer_init(), the xdelay() functions return immediately.
We need to call timer_init() early, so that these functions work and
the PHY and DDR init code works correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-23 08:30:58 +02:00
Anton Schubert
e863f7f051 arm: mvebu: add Armada XP SATA support
This patch initializes the SATA address windows on Armada XP and
allows it to work with the existing mvsata_ide driver.
It also adds the necessary configuration for the db-mv784mp-gp board.

Signed-off-by: Anton Schubert <anton.schubert@gmx.de>
Tested-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-23 08:30:58 +02:00
Stefan Roese
fe11ae2437 usb: Add EHCI support for Armada 38x (mvebu)
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.

Tested on DB-88F6280-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10 14:55:50 +02:00
Stefan Roese
4d991cb3c7 arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x
This patch adds support for the common AHCI controller on the Marvell
Armada 38x.

Tested on the Marvell DB-88F6820-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10 14:55:50 +02:00
Stefan Roese
7f1adcd74f arm: mvebu: Add SDIO/SDHCI support for Armada A38x
Armada A38x implements an SDHCI compatible SDIO controller. This patch
enables the Marvell driver to support this SoC. And enables the
SDIO controller if selected by the board configuration.

Tested on Marvell DB-88F6820-GP board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-07-10 14:54:09 +02:00
Kevin Smith
e1b078e06c arm: mvebu: Update CBAR with SOC regs base
SMP-enabled Linux kernels read the CBAR register in CP15 to find
the address of the SCU registers.  After remapping internal
registers, also update the CBAR so the kernel can find them.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
2015-06-14 17:48:28 +02:00
Stefan Roese
5730360efc arm: mvebu: Disable L2 cache before enabling d-cache
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
2015-06-14 17:48:28 +02:00
Stefan Roese
2083db7a75 arm: mvebu: Remove "u-boot.kwb" CONFIG_BUILD_TARGET for non-SPL targets
By removing this default build target, the "u-boot.kwb" target is not
automatically generated. This fixes a temporary build error when using
out-of-tree builds, as buildman does per default (reported by Simon).

When the full SPL support is added for these targets with the DDR training
code, the "u-boot-spl.kwb" image will be generated automatically.

Users providing a special bin_hdr binary (binary.0) file can always add
this binary file and generate the full firmware image by issuing the
"make u-boot.kwb" command directly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-05-05 14:32:05 +02:00
Stefan Roese
60b75324ea arm: mvebu: Add d-cache invalidate before enabling the d-cache
This solves some RX problems that have been seen, when using the
mvneta ethernet driver. The cache needs to be reset into a "clean"
state before using it.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:32:04 +02:00
Stefan Roese
e89bf8bcc9 arm: mvebu: Remove coherency configuration
We are not using the coherency feature in U-Boot at all. So lets remove
this configuration from the mbus driver.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:32:04 +02:00
Stefan Roese
cae9008f69 arm: mvebu: Change network init code to allow a more flexible setup
With the introduction of the Armada 38x support, its necessary to change
the mvneta ethernet driver init call from always 4 times to a
configurable value. Lets make this init call more flexible by moving
the actually used devices to the config header.

Additionally this patch takes care of the slightly different base
addresses for the ethernet controllers on A38x.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-05-05 14:31:49 +02:00
Stefan Roese
9c6d3b7b66 arm: mvebu: Add basic Armada 38x support
This patch adds support for the Marvell Armada 38x SoC family.

Supported peripherals are:
- UART
- Ethernet (mvneta)
- I2C
- SPI (including SPI NOR flash)

Tested on Marvell DB-88F6820-GP evaluation board.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
880b15a37b arm: mvebu: Move CONFIG_SPL_LDSCRIPT to common header
This way, new MVEBU boards don't need to specifiy the common location
for the SPL linker script.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
f7c0ef073d arm: mvebu: Only define MV88F78X60 for Armada XP
This define is used by the DDR training code for Armada XP. With the
upcoming addition of Armada 38x support, lets only define it for
Armada XP in this common header.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
8402b69b7e arm: mvebu: Remove unreferenced define
MAX_MVNETA_DEVS is not used anywhere in U-Boot. So lets remove it.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
250eea74b9 arm: mvebu: Change header macros from ARMADA_XP to MVEBU
Since these files will be used for other MVEBU SoC's, lets reflect this
in the headers marcos as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
d078765640 arm: mvebu: Move mvebu-common into mach-mvebu
Now that the mach-mvebu directory exists and is used by Armada XP we can
move the mvebu-common files into this directory as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
8cb7872230 arm: armada-xp: Move SoC headers to mach-mvebu/include/mach
Move arch/arm/include/asm/arch-armada-xp/*
     -> arch/arm/mach-mvebu/include/mach/*

Additionally the SYS_SOC is renamed from "armada-xp" to "mvebu". With this
change all these files can better be shared with other, newer Mavell
MVEBU SoC's. Like the upcoming Armada 38x support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00
Stefan Roese
350b50eea3 arm: armada-xp: Move SoC sources to mach-mvebu
Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/*

Since this platform will be extended to support other Marvell SoC's as
well, lets rename it directly to mvebu.

This will be used by the upcoming Armada 38x suport (A38x).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2015-05-05 14:28:29 +02:00