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arm: mvebu: Enable L2 cache on Armada XP

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Until now, the L2 cache was never enabled again in U-Boot. To get
even better performance (bootup time), lets enable the L2 cache
in U-Boot. This code was taken from the Linux kernel.

A performance gain was measured on the DB-MV784MP-GP board by testing
with tftpboot and sata commands.

This patch also cleans up the L2 cache related code. And makes sure that
the L2 cache is only disabled once.

Please note that A38x still runs with L2 cache disabled. And needs
to be enabled for this SoC in a separate patch if needed or desired.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Stefan Roese 2015-12-03 12:39:45 +01:00
parent af2728abe6
commit 3e5ce7ceeb
1 changed files with 25 additions and 9 deletions
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34
arch/arm/mach-mvebu/cpu.c
View file

@ -389,20 +389,36 @@ void scsi_init(void)
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
/* First disable L2 cache - may still be enable from BootROM */
if (mvebu_soc_family() == MVEBU_SOC_A38X)
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
/* Avoid problem with e.g. neta ethernet driver */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
if (mvebu_soc_family() == MVEBU_SOC_AXP) {
u32 u;
/*
* For Aurora cache in no outer mode, enable via the CP15
* coprocessor broadcasting of cache commands to L2.
*/
asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
u |= BIT(8); /* Set the FW bit */
asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
isb();
/* Enable the L2 cache */
setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
}