This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
The NAND flash controller of MT7621 supports only SLC NAND flashes.
It supports 4~12 bits correction with maximum 4KB page size.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds GMAC support for MediaTek MT7621 SoC.
MT7621 has the same GMAC/Switch configuration as MT7623.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The address returned by regmap_get_range() is not remapped. Directly r/w
to this address is ok for ARM platforms since it's idential to the virtual
address.
But for MIPS platform only virtual address should be used for access.
To solve this issue, the regmap api regmap_read/regmap_write should be used
since they will remap address before accessing.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The iobase address from dts node is actually physical address. It's
identical to the virtual address in ARM platform. This is ok because this
driver was used only by ARM platforms (mt7622/mt7623 ...).
But now this driver will be used by mt7621 which is a MIPS SoC. For MIPS
platform the physical address space is mapped to KSEG0 and KSEG1 and this
makes the virtual address apparently not idential to its physical address.
To solve this issue, this patch replaces dev_read_addr with dev_remap_addr
to get the remapped iobase address.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch makes mt7621_wdt driver available for MediaTek MT7621 SoC
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch makes mt7621_gpio driver available for MediaTek MT7621 SoC
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds pinctrl support for MediaTek MT7621 SoC.
The MT7621 SoC supports pinconf, but it is not the same as mt7628.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
- Add OP-TEE nodes for stm32mp13x, alligned with upstreamed OP-TEE
- Introduce of_to_plat ops in stm32_sdmmc2 driver
- Activate more features in stm32mp13 defconfig and support of STM32MP13x Rev.Y
- Drop fastboot and stm32prog trigger gpios on STM32MP15x DHCOM board
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Merge tag 'u-boot-stm32-20220712' of https://source.denx.de/u-boot/custodians/u-boot-stm
- Alignment with Linux kernel device tree v5.19 for stm32mp15 and stm32mp13
- Add OP-TEE nodes for stm32mp13x, alligned with upstreamed OP-TEE
- Introduce of_to_plat ops in stm32_sdmmc2 driver
- Activate more features in stm32mp13 defconfig and support of STM32MP13x Rev.Y
- Drop fastboot and stm32prog trigger gpios on STM32MP15x DHCOM board
ISP1760/61/63 are a family of usb controllers, here the main
goal is to support the ISP1763 hcd part found in the MPS3 FPGA
board form Arm. This is based on the kernel driver and ported
to u-boot.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Move urb code from musb only use to a more common scope, so other
drivers in the future can use the handling of urb in usb.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
When usb PHY initialization is done, the PHY need to be reset.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
New IP adds a conditional reset that impact the clock
error management. It is now linked to a new compatible.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The stm32mp13 soc differs from the stm32mp15 in terms of
clear register offset for controlling the FMP (Fast Mode Plus).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add support for new compatible st,stm32mp1-rcc-secure used when the
RCC resource is managed by secured world (RCC_TZCR.TZEN=1)
iand when SCMI is used.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add the uclass ops of_to_plat to parse the device tree properties
to respect the expected sequence by the driver model.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
All the elements of privdata are static and build from device tree,
they are moved in platdata to prepare the support of ops
of_to_plat.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all other functions
in SDMMCv2 driver
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Ic51acdfbbba6e971809c1029dd2227038bfe879d
Commit d293759d55 ("serial: ns16550: Add support for
SPL_DEBUG_UART_BASE") fixed support for setting correct early debug UART
base address in SPL.
But after this commit, output from Marvell A385 BootROM is truncated or
lost and not fully present on serial console.
Debugging this issue showed that BootROM just put bytes into UART HW output
buffer and does not wait until UART HW transmit all characters. U-Boot
ns16550 early debug is initialized very early and during its initialization
is resetting UART HW and flushing remaining transmit buffer (which still
contains BootROM output).
Fix this issue by waiting in init function prior resetting UART HW until
TxEmpty bit in UART Line Status Register is set. TxEmpty is set when all
remaining bytes from HW buffer are transmitted.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
[trini: Add comment, move ';' to new line per checkpatch.pl]
Signed-off-by: Tom Rini <trini@konsulko.com>
The top level DT node of pwm-leds is not a LED itself, bind NOP uclass
driver to it, and bind different LED uclass driver to its subnodes which
represent the actual LEDs. This change removes the top-level node from
the 'led list' command output and is based on the commit 0107469780
("led: gpio: Use NOP uclass driver for top-level node").
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
With the current code if the board has an ONFI compliant NAND without
support to the get and set features, U-boot returns an ENOTSUP error when
trying to tune the timings which prevents the probe of the device.
Indeed onfi_set_features() return ENOTSUP error if set/get features is not
supported. In the case of timings we should not return ENOTSUP because we
can use the default timings. The NAND is already capable of listening at
its highest supported rate, so we assume in this case that it is fine to
skip the operation.
Fix it by adding an intermediate nand_onfi_set_timings() function which
does not error out if set/get feature is not supported.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
sandbox_defconfig builds the DA7219 driver. It should be possible to
build the sandbox without ACPI support.
ACPI support in the DA7219 driver is only needed when creating an ACPI
table. Fix building with ACPIGEN=n.
Fixes: 0324b7123e ("sound: Add an ACPI driver for Dialog Semicondutor da7219")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
sandbox_defconfig builds the max98357a driver. It should be possible to
build the sandbox without ACPI support.
ACPI support in the max98357a driver is only needed when creating an ACPI
table. Fix building with ACPIGEN=n.
Fixes: 54bcca2973 ("sound: Add an ACPI driver for Maxim MAX98357ac")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
With the last platform for this architecture removed, remove the rest of
the architecture support as well.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
At this point, the only user of ohci-hcd that also uses PCI is using DM,
so we can drop CONFIG_PCI_OHCI* usage. No platforms set either of
CONFIG_SYS_USB_OHCI_BOARD_INIT or CONFIG_SYS_USB_OHCI_CPU_INIT so those
hooks can be removed as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SYS_OHCI_SWAP_REG_ACCESS
CONFIG_SYS_USB_OHCI_CPU_INIT
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
CONFIG_SYS_USB_OHCI_SLOT_NAME
CONFIG_USB_ATMEL
CONFIG_USB_ATMEL_CLK_SEL_PLLB
CONFIG_USB_ATMEL_CLK_SEL_UPLL
CONFIG_USB_OHCI_LPC32XX
CONFIG_USB_OHCI_NEW
Signed-off-by: Tom Rini <trini@konsulko.com>
Tighten up symbol dependencies in a number of places. Ensure that a SPL
specific option has at least a direct dependency on SPL. In places
where it's clear that we depend on something more specific, use that
dependency instead. This means in a very small number of places we can
drop redundant dependencies.
Reported-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.
Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:
ofnode node;
dev_for_each_subnode(node, parent) {
struct udevice *dev;
int ret;
ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
}
However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.
Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.
Select MISC as the controller driver is implemented as a misc device.
Signed-off-by: Joel Stanley <joel@jms.id.au>
