The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is enough.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
0x400 is true 1K.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.
This makes our MAC address generation code also work on sun6i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
For sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a function to retreive the sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Colombus defconfig settings are missing a number of settings for recently
added features, because we did not know exactly how things were hooked up.
Maxime Ripard has run various tests to get us the necessary details, this
commit updates the defconfig with this info.
This commit also updates the dram clk and zq values with values verified
by Maxime to be the ones used by the original firmware for this board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Add netargs and netboot option.
* This enables tftp and nfs booting
* This puts omap5 devices inline with other devices such as am335x and am437x
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
AM43xx Industrial Development Kit is a new board
based on AM437x line of SoCs. Targetted at Industrial
Automation applications, it comes with EtherCAT, motor
control and other goodies.
Thanks to James Doublesin for all the help.
Cc: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This regulator is used with AM437x IDK to feed
VDD_MPU, without means to scale VDD_MPU we can't
support higher frequencies.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Make sure that all OPPs are checked on
scale_vcores(). While at that also fix 600MHz
VDD_MPU voltage according to AM437x Data Manual
available at [1].
Table 5-3 on that document, lists all valid
voltages per frequency.
[1] http://www.ti.com/lit/ds/symlink/am4379.pdf
Signed-off-by: Felipe Balbi <balbi@ti.com>
DCDC1 is used as VDD_MPU in all known boards,
let's define all other valid voltages for that
rail so it can be used by our boards.
Signed-off-by: Felipe Balbi <balbi@ti.com>
The frequencies for 25MHz in dpll_per were out of spec for 25MHz,
correct.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values. Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.
Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Need to provide PLL values for all possible input frequencies (19.2, 24,
25, 26MHz). Values provide are also optimized for jitter (needed
especially for PER PLL and DDR PLL).
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.
The current implementation has two limitations:
a) it only works in 8-bit mode
b) it only supports read access
Both is easily fixable by someone who has hardware to implement it.
Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.
Tested on AM335x hardware.
Tested-by: Guido Martínez <guido@vanguardiasur.com.ar>
Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar>
Signed-off-by: Daniel Mack <zonque@gmail.com>
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini <trini@ti.com>
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment
like qemu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.
Update the documentation to list some of the available commands.
This does not support fixed MTRRs as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.
Signed-off-by: Simon Glass <sjg@chromium.org>
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.
Signed-off-by: Simon Glass <sjg@chromium.org>
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.
Signed-off-by: Simon Glass <sjg@chromium.org>
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.
We set RAM as cacheable (with write-back) and registers as non-cacheable.
Signed-off-by: Simon Glass <sjg@chromium.org>
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Signed-off-by: Simon Glass <sjg@chromium.org>
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).
Signed-off-by: Simon Glass <sjg@chromium.org>
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
