For USB device-tree fix-up to work properly, its necessary to
mention USB1 options before that of USB2 inside default hwconfig
string
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Current IFC timings for NAND flash are not able to support existing
K9F1G08U0B and new K9F1G08U0D flash.
so Update the timings to support both.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.
QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
1. Confirm whether QSGMII Riser Card is used.
2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.
However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
SGMII5/6 and SGMII7/8 are not on the same slot on P5040
according to the serdes protocol.
So it is not proper to organize SGMII5/6 and SGMII7/8
on one bus and SGMII5/6 can't work.
So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for
SGMII5/6
Signed-off-by: Zhao Qiang <B45475@freescale.com>
CHASSIS2 architecture never fix clock groups for Cluster and hardware
accelerator like PME, FMA. These are SoC defined. SoC defines :-
- NUM of PLLs present in the system
- Clusters and their Clock group
- hardware accelerator and their clock group
if no clock group, then platform clock divider for FMAN, PME
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
T1040 SoC has
- DDR controller ver 5.0
- 2 PLLs
- 8 IFC Chip select
- FMAN Muram 192K
- No Srio
- Sec controller ver 5.0
- Max CPU update for its personalities
So, update the defines accordingly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CHASSIS2 architecture never defines type of L2 cache present in SoC.
it is dependent upon the core present in the SoC.
for example,
- e6500 core has L2 cluster (Kibo)
- e5500 core has Backside L2 Cache
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
DDR parameters clk_adjust were changed. This can make the DDR
run more stable. The new value were gotten by the DDR testing
tool.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
This patch re-config the NOR flash timing parameters which could make
the ifc timing more flexible for NOR flash.
The new parameters could fix the problem of hanging at "Flash:"
occasionally when booting the board.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
The patch:
"blackfin: Move blackfin watchdog driver out of the blackfin arch folder."
(sha1: e9a389a184)
changed hw_watchdog_init() prototype which didn't match
with Microblaze one.
This patch fixes the driver and Microblaze initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This bug was introduced by:
"Add GPL-2.0+ SPDX-License-Identifier to source files"
(sha1: 1a4596601f)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
commit 39ac34473f ("cmd_mtdparts: use 64
bits for flash size, partition size & offset") introduced warnings
in a couple places due to printf formats or pointer casting.
This patch fixes the warnings pointed out here:
http://lists.denx.de/pipermail/u-boot/2013-October/164981.html
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Tom Rini <trini@ti.com>
If dout buffer is not 32 bit-aligned or data to transmit is not multiple
of 32 bit the read data pointer is already incremented on single byte reads.
Signed-off-by: Timo Herbrecher <t.herbrecher@gateware.de>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
As the spi flash transfer to multiple parts, it is forgot to add
Atmel AT25DF321 spi flash support, which broken several Atmel EK
boards which this chip. So, add it
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Added GPL-2.0+ SPDX-License-Identifier for missed sf
source files.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
python used in buildman doesn't need to be placed in
/usr/bin/python, So use env to ensure that the interpreter
will pick the python from environment.
Usefull with several versions of python's installed on system.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Pass a valid cmdtp into do_tftpb(), do_ext2load(), and do_get_fat(), to
avoid possible crashes due to null pointer dereferencing.
Commit d7884e047d does not go far enough.
There is still at least one call chain that can result in a crash.
The do_tftpb(), do_ext2load(), and do_get_fat() functions expect a valid
cmdtp. Passing in NULL is particularly bad in the do_tftpb() case,
because eventually boot_get_kernel() will be called with a NULL cmdtp:
do_tftpb() -> netboot_common() -> bootm_maybe_autostart() -> do_bootm()
-> do_bootm_states() -> bootm_find_os() -> boot_get_kernel()
Around line 991 in cmd_bootm.c, boot_get_kernel() will dereference the
null pointer, and the board will crash.
Signed-off-by: Steven A. Falco <stevenfalco@gmail.com>
Add a MAC address create based on the OMAP die ID registers.
Then poplulate the ethaddr enviroment variable so that the device
tree alias can be updated prior to boot.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
commit d196bd8803 adds
redundand environment to mmc. The usage of malloc in
env_relocate_spec triggers cache errors on armv7.
Tested on a not mainlined i.MX53 board:
Board: TQMa53
I2C: ready
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
ERROR: v7_dcache_inval_range - start address is not aligned - 0x8f57c2d8
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x8f57e2d8
ERROR: v7_dcache_inval_range - start address is not aligned - 0x8f57e2e0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x8f5802e0
Using default environment
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
As the SPI controller is not initialized before env_init(), it causes
reading env in dataflash failed. So, although saveenv() successfully,
it shows warning information when reboot the system as following:
*** Warning - bad CRC, using default environment
Let the env_relocate() to check env CRC and import it.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory
part.
The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron
so the timings needs to be updated
Signed-off-by: Dan Murphy <dmurphy@ti.com>
In [1] we discussed how we should deal with dual (or, more generally,
multiple) licensed files. Add this to Licenses/README so it's
properly documented.
[1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/166518
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Add the word 'list' to the end of the line, per Stephen Warren's
feedback]
Signed-off-by: Tom Rini <trini@ti.com>
When a toolchain invocation fails, an exception is thrown but not caught
which then aborts the entire toolchain detection process. To solve this,
request that exceptions not be thrown, since the toolchain init code
already error-checks the command result. This solves e.g.:
- found '/usr/bin/winegcc'
Traceback (most recent call last):
...
Exception: Error running '/usr/bin/winegcc --version'
Change-Id: I579c72ab3b021e38b14132893c3375ea257c74f0
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(formatted to 80cols)
The musb driver defines and uses MUSB_CSR0_H_DIS_PING, however this
bit is reserved on the DM36x. Thus this patch ensures that the
reserved bit is not accesssed.
It has been observed that some USB devices will fail to enumerate
with errors such as 'error in inquiry' without this patch.
See http://www.ti.com/litv/pdf/sprufh9a for details.
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Acked-by: Marek Vasut <marex@denx.de>
OMAP5 boards may have both eMMC (on MMC2) and an SD slot (on MMC1). We
Update the default bootcmd to match what happens on AM335x where we try
SD first, and then eMMC. In this case however, the hardware layout used
for powering both of these means that in the kernel eMMC shall be found
first as it is powered by a fixed regulator and SD found second as SD is
powered via the palmas which will result in deferred probing.
Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
This allows you to write data to an UBI volume when the amount of memory
available to write that data from is less than the total size of the
data. For example, you may split a root filesystem UBIFS image into
parts, provide the total size of the image to the first write.part
command and then use multiple write.part commands to write the
subsequent parts of the volume. This results in a sequence of commands
akin to:
ext4load mmc 0:1 0x80000000 rootfs.ubifs.0
ubi write.part 0x80000000 root 0x08000000 0x18000000
ext4load mmc 0:1 0x80000000 rootfs.ubifs.1
ubi write.part 0x80000000 root 0x08000000
ext4load mmc 0:1 0x80000000 rootfs.ubifs.2
ubi write.part 0x80000000 root 0x08000000
This would write 384MiB of data to the UBI volume 'root' whilst only
requiring 128MiB of said data to be held in memory at a time.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
int64_t matches the bytes field in struct ubi_mkvol_req to which the
size is assigned. With the prior signed 32 bit integer, volumes were
restricted to being less than 2GiB in size.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
This matches the 64 bit size in struct mtd_info and allows the mtdparts
command to function correctly with a flash >= 4GiB. Format specifiers
for size & offset are given the ll length, matching its use in
drivers/mtd in absence of something like inttypes.h/PRIx64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
Linux modified the MTD driver interface in commit edbc4540 (with the
same name as this commit). The effect is that calls to mtd_read will
not return -EUCLEAN if the number of ECC-corrected bit errors is below
a certain threshold, which defaults to the strength of the ECC. This
allows -EUCLEAN to stop indicating "some bits were corrected" and begin
indicating "a large number of bits were corrected, the data held in
this region of flash may be lost soon". UBI makes use of this and when
-EUCLEAN is returned from mtd_read it will move data to another block
of flash. Without adopting this interface change UBI on U-boot attempts
to move data between blocks every time a single bit is corrected using
the ECC, which is a very common occurance on some devices.
For some devices where bit errors are common enough, UBI can get stuck
constantly moving data around because each block it attempts to use has
a single bit error. This condition is hit when wear_leveling_worker
attempts to move data from one PEB to another in response to an
-EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
called to perform the data copy, and after the data is written it is
read back to check its validity. If that read returns UBI_IO_BITFLIPS
(in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
wear_leveling worker, which then proceeds to schedule the destination
PEB for erasure. This leads to erase_worker running on the PEB, and
following a successful erase wear_leveling_worker is called which
begins this whole cycle all over again. The end result is that (without
UBI debug output enabled) the boot appears to simply hang whilst in
reality U-boot busily works away at destroying a block of the NAND
flash. Debug output from this situation:
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
UBI: fixable bit-flip detected at PEB 1027
UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
UBI: fixable bit-flip detected at PEB 4083
UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
UBI DBG: erase_worker: erase PEB 4083 EC 55
UBI DBG: sync_erase: erase PEB 4083, old EC 55
UBI DBG: do_sync_erase: erase PEB 4083
UBI DBG: sync_erase: erased PEB 4083, new EC 56
UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
...
This patch adopts the interface change as in Linux commit edbc4540 in
order to avoid such situations. Given that none of the drivers under
drivers/mtd return -EUCLEAN, this should only affect those using
software ECC. I have tested that it works on a board which is
currently out of tree, but which I hope to be able to begin
upstreaming soon.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
