This driver should only compile if CONFIG_MPC8XXX_SPI is set
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board.
This board has an ST M25P40 4Mbit EEPROM on its SPI bus
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
clean up the cache config from configs.h of board
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the
currently-defined 83xx boards. This change guarantees that the environment
will be located on the first flash sector after the U-Boot image.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether
to update TSEC1's device-tree node, so we need to add it
to all the boards with TSECs. Do this for 83xx and 86xx, too,
since they will eventually do something similar.
Signed-off-by: Andy Fleming <afleming@freescale.com>
The tsec_info structure and array has a "flags" field for each
ethernet controller. This field is the only reason there are
settings. Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: Andy Fleming <afleming@freescale.com>
this enables libfdt code by default for the
freescale mpc8313erdb, mpc832xemds, mpc8349emds,
mpc8349itx and gp boards.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h
used to be included but CONFIG_BOOTP_MASK was not defined.
Remove lingering references to CFG_CMD_* symbols.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM
Were not being used when setting the appropriate register
Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM
To allow full config of the SCCR.
Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.
Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Signed-off-by: Timur Tabi <timur@freescale.com>
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: Timur Tabi <timur@freescale.com>
add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
STDOUT_PATH configuration bits to mpc8349emds,
mpc8349itx, and mpc8360emds board code.
redo environment to use bootm with the fdtaddr
for booting ARCH=powerpc kernels by default,
and provide default fdtaddr values.
Hello,
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.
/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
CHANGELOG:
Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.
regards,
Ben
- Removed MPC8349ADS port
- Added PCI support to MPC8349ADS
- reworked memory map to allow mapping of all regions with BATs
Patch by Kumar Gala 20 Apr 2006
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
