mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xx
This commit is contained in:
Wolfgang Denk
commit
1d55483cf7
39 changed files with 473 additions and 272 deletions
30
MAINTAINERS
30
MAINTAINERS
|
|
@ -42,6 +42,10 @@ Yuli Barcohen <yuli@arabellasw.com>
|
|||
Rattler MPC8248
|
||||
ZPC1900 MPC8265
|
||||
|
||||
Michael Barkowski <michael.barkowski@freescale.com>
|
||||
|
||||
MPC8323ERDB MPC8323
|
||||
|
||||
Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
|
||||
|
||||
sacsng MPC8260
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||||
|
|
@ -217,6 +221,10 @@ The LEOX team <team@leox.org>
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|||
|
||||
ELPT860 MPC860T
|
||||
|
||||
Dave Liu <daveliu@freescale.com>
|
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|
||||
MPC8360EMDS MPC8360
|
||||
|
||||
Nye Liu <nyet@zumanetworks.com>
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||||
|
||||
ZUMA MPC7xx_74xx
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||||
|
|
@ -273,6 +281,10 @@ Denis Peter <d.peter@mpl.ch>
|
|||
MIP405 PPC4xx
|
||||
PIP405 PPC4xx
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||||
|
||||
Kim Phillips <kim.phillips@freescale.com>
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||||
|
||||
MPC8349EMDS MPC8349
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||||
|
||||
Daniel Poirot <dan.poirot@windriver.com>
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||||
|
||||
sbc8240 MPC8240
|
||||
|
|
@ -321,6 +333,11 @@ Peter De Schrijver <p2@mind.be>
|
|||
|
||||
ML2 PPC4xx
|
||||
|
||||
Timur Tabi <timur@freescale.com>
|
||||
|
||||
MPC8349E-mITX MPC8349
|
||||
MPC8349E-mITX-GP MPC8349
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||||
|
||||
Erik Theisen <etheisen@mindspring.com>
|
||||
|
||||
W7OLMC PPC4xx
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||||
|
|
@ -353,19 +370,6 @@ John Zhan <zhanz@sinovee.com>
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|||
|
||||
svm_sc8xx MPC8xx
|
||||
|
||||
Timur Tabi <timur@freescale.com>
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||||
|
||||
MPC8349E-mITX MPC8349
|
||||
MPC8349E-mITX-GP MPC8349
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||||
|
||||
Kim Phillips <kim.phillips@freescale.com>
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|
||||
MPC8349EMDS MPC8349
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|
||||
Dave Liu <daveliu@freescale.com>
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|
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MPC8360EMDS MPC8360
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|
||||
-------------------------------------------------------------------------
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Unknown / orphaned boards:
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|
|
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1
MAKEALL
1
MAKEALL
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|
@ -299,6 +299,7 @@ LIST_8260=" \
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|||
LIST_83xx=" \
|
||||
MPC8313ERDB_33 \
|
||||
MPC8313ERDB_66 \
|
||||
MPC8323ERDB \
|
||||
MPC832XEMDS \
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||||
MPC8349EMDS \
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MPC8349ITX \
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||||
|
|
|
|||
10
Makefile
10
Makefile
|
|
@ -1688,7 +1688,7 @@ MPC8313ERDB_66_config: unconfig
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echo -n "...66M..." ; \
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echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
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fi ;
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@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
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@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
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|
||||
MPC8323ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
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|
|
@ -1716,10 +1716,10 @@ MPC832XEMDS_SLAVE_config: unconfig
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echo -n "...66M..." ; \
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echo "#define PCI_66M" >>$(obj)include/config.h ; \
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fi ;
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@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
|
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@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
|
||||
|
||||
MPC8349EMDS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale
|
||||
|
||||
MPC8349ITX_config \
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||||
MPC8349ITX_LOWBOOT_config \
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|
|
@ -1733,7 +1733,7 @@ MPC8349ITXGP_config: unconfig
|
|||
@if [ "$(findstring LOWBOOT,$@)" ] ; then \
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echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx
|
||||
@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
|
||||
|
||||
MPC8360EMDS_config \
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MPC8360EMDS_HOST_33_config \
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||||
|
|
@ -1758,7 +1758,7 @@ MPC8360EMDS_SLAVE_config: unconfig
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echo -n "...66M..." ; \
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echo "#define PCI_66M" >>$(obj)include/config.h ; \
|
||||
fi ;
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@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
|
||||
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
|
||||
|
||||
sbc8349_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
|
||||
|
|
|
|||
102
board/freescale/common/pq-mds-pib.c
Normal file
102
board/freescale/common/pq-mds-pib.c
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
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||||
*
|
||||
* Tony Li <tony.li@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation;
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||||
*/
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||||
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||||
#include <common.h>
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||||
#include <i2c.h>
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#include <asm/io.h>
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||||
|
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#include "pq-mds-pib.h"
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||||
|
||||
int pib_init(void)
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||||
{
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u8 val8;
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u8 orig_i2c_bus;
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||||
|
||||
/* Switch temporarily to I2C bus #2 */
|
||||
orig_i2c_bus = i2c_get_bus_num();
|
||||
i2c_set_bus_num(1);
|
||||
|
||||
val8 = 0;
|
||||
#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
|
||||
/* Assign PIB PMC slot to desired PCI bus */
|
||||
i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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||||
val8 = 0xff;
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||||
i2c_write(0x23, 0x2, 1, &val8, 1);
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||||
i2c_write(0x23, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
||||
val8 = 0x34;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
#if defined(CONFIG_MPC832XEMDS)
|
||||
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
|
||||
#else
|
||||
val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
|
||||
#endif
|
||||
i2c_write(0x26, 0x2, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x26, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x27, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x27, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x27, 0x2, 1, &val8, 1);
|
||||
val8 = 0xef;
|
||||
i2c_write(0x27, 0x3, 1, &val8, 1);
|
||||
|
||||
eieio();
|
||||
|
||||
#if defined(CONFIG_MPC832XEMDS)
|
||||
printf("PCI 32bit bus on PMC2 &PMC3\n");
|
||||
#else
|
||||
printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PQ_MDS_PIB_ATM)
|
||||
#if defined(CONFIG_MPC8360EMDS)
|
||||
val8 = 0;
|
||||
i2c_write(0x20, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x20, 0x7, 1, &val8, 1);
|
||||
|
||||
val8 = 0xdf;
|
||||
i2c_write(0x20, 0x2, 1, &val8, 1);
|
||||
val8 = 0xf7;
|
||||
i2c_write(0x20, 0x3, 1, &val8, 1);
|
||||
|
||||
eieio();
|
||||
|
||||
printf("QOC3 ATM card on PMC0\n");
|
||||
#elif defined(CONFIG_MPC832XEMDS)
|
||||
val = 0;
|
||||
i2c_write(0x26, 0x7, 1, &val, 1);
|
||||
val = 0xf7;
|
||||
i2c_write(0x26, 0x3, 1, &val, 1);
|
||||
|
||||
val = 0;
|
||||
i2c_write(0x21, 0x6, 1, &val, 1);
|
||||
i2c_write(0x21, 0x7, 1, &val, 1);
|
||||
|
||||
val = 0xdf;
|
||||
i2c_write(0x21, 0x2, 1, &val, 1);
|
||||
val = 0xef;
|
||||
i2c_write(0x21, 0x3, 1, &val, 1);
|
||||
|
||||
eieio();
|
||||
|
||||
printf("QOC3 ATM card on PMC1\n");
|
||||
#endif
|
||||
#endif
|
||||
/* Reset to original I2C bus */
|
||||
i2c_set_bus_num(orig_i2c_bus);
|
||||
return 0;
|
||||
}
|
||||
9
board/freescale/common/pq-mds-pib.h
Normal file
9
board/freescale/common/pq-mds-pib.h
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation;
|
||||
*/
|
||||
|
||||
extern int pib_init(void);
|
||||
|
|
@ -23,7 +23,11 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
#include <pci.h>
|
||||
#include <mpc83xx.h>
|
||||
|
||||
|
|
@ -96,21 +100,22 @@ void pci_init_board(void)
|
|||
mpc83xx_pci_init(1, reg, warmboot);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p) {
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
@ -112,8 +112,6 @@ long int initdram(int board_type)
|
|||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
puts("Initializing\n");
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
msize = fixed_sdram();
|
||||
|
||||
|
|
@ -127,7 +125,6 @@ long int initdram(int board_type)
|
|||
resume_from_sleep();
|
||||
#endif
|
||||
|
||||
puts(" DDR RAM: ");
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return msize;
|
||||
}
|
||||
|
|
@ -17,7 +17,6 @@
|
|||
#include <miiphy.h>
|
||||
#include <command.h>
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#endif
|
||||
|
|
@ -92,8 +91,6 @@ long int initdram(int board_type)
|
|||
|
||||
msize = fixed_sdram();
|
||||
|
||||
puts("\n DDR RAM: ");
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -185,33 +182,21 @@ void pci_init_board(void)
|
|||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
|
||||
/*
|
||||
* Prototypes of functions that we use.
|
||||
*/
|
||||
void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void ft_pci_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int nodeoffset;
|
||||
int tmp[2];
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/memory");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
||||
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
||||
fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o pci.o
|
||||
COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
@ -29,6 +29,11 @@
|
|||
#endif
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
#if defined(CONFIG_PQ_MDS_PIB)
|
||||
#include "../common/pq-mds-pib.h"
|
||||
#endif
|
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
|
|
@ -86,6 +91,14 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_PQ_MDS_PIB
|
||||
pib_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fixed_sdram(void);
|
||||
|
||||
long int initdram(int board_type)
|
||||
|
|
@ -101,8 +114,6 @@ long int initdram(int board_type)
|
|||
|
||||
msize = fixed_sdram();
|
||||
|
||||
puts("\n DDR RAM: ");
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -155,22 +166,22 @@ int checkboard(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
@ -20,6 +20,8 @@
|
|||
#include <i2c.h>
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
|
||||
#include <asm/fsl_i2c.h>
|
||||
|
|
@ -129,7 +131,6 @@ void pci_init_board(void)
|
|||
volatile pcictrl83xx_t *pci_ctrl;
|
||||
volatile pciconf83xx_t *pci_conf;
|
||||
|
||||
u8 val8, orig_i2c_bus;
|
||||
u16 reg16;
|
||||
u32 val32;
|
||||
u32 dev;
|
||||
|
|
@ -197,43 +198,6 @@ void pci_init_board(void)
|
|||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
|
||||
PIWAR_IWS_2G;
|
||||
|
||||
/*
|
||||
* Assign PIB PMC slot to desired PCI bus
|
||||
*/
|
||||
|
||||
/* Switch temporarily to I2C bus #2 */
|
||||
orig_i2c_bus = i2c_get_bus_num();
|
||||
i2c_set_bus_num(1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x23, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x23, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x23, 0x2, 1, &val8, 1);
|
||||
i2c_write(0x23, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
||||
val8 = 0x34;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
|
||||
val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
|
||||
i2c_write(0x26, 0x2, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x26, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x27, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x27, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x27, 0x2, 1, &val8, 1);
|
||||
val8 = 0xef;
|
||||
i2c_write(0x27, 0x3, 1, &val8, 1);
|
||||
asm("eieio");
|
||||
|
||||
/* Reset to original I2C bus */
|
||||
i2c_set_bus_num(orig_i2c_bus);
|
||||
|
||||
/*
|
||||
* Release PCI RST Output signal
|
||||
*/
|
||||
|
|
@ -290,8 +254,6 @@ void pci_init_board(void)
|
|||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
|
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
|
||||
|
||||
printf("PCI 32bit bus on PMC2 & PMC3\n");
|
||||
|
||||
/*
|
||||
* Hose scan.
|
||||
*/
|
||||
|
|
@ -299,7 +261,27 @@ void pci_init_board(void)
|
|||
}
|
||||
#endif /* CONFIG_PCISLAVE */
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(hose[0].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
|
@ -34,6 +34,8 @@
|
|||
#endif
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
|
||||
int fixed_sdram(void);
|
||||
|
|
@ -68,8 +70,6 @@ long int initdram (int board_type)
|
|||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
puts("Initializing\n");
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
|
|
@ -88,7 +88,7 @@ long int initdram (int board_type)
|
|||
*/
|
||||
ddr_enable_ecc(msize * 1024 * 1024);
|
||||
#endif
|
||||
puts(" DDR RAM: ");
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -189,9 +189,6 @@ void sdram_init(void)
|
|||
volatile lbus83xx_t *lbc= &immap->lbus;
|
||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||
|
||||
puts("\n SDRAM on Local Bus: ");
|
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
|
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
|
||||
*/
|
||||
|
|
@ -253,26 +250,25 @@ void sdram_init(void)
|
|||
#else
|
||||
void sdram_init(void)
|
||||
{
|
||||
puts(" SDRAM on Local Bus is NOT available!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
@ -25,6 +25,12 @@
|
|||
#include <pci.h>
|
||||
#include <asm/mpc8349_pci.h>
|
||||
#include <i2c.h>
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -382,7 +388,40 @@ pci_init_board(void)
|
|||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
#ifdef CONFIG_MPC83XX_PCI2
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
|
||||
tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
|
@ -39,6 +39,8 @@
|
|||
#endif
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPD_EEPROM
|
||||
|
|
@ -74,7 +76,7 @@ int fixed_sdram(void)
|
|||
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
|
||||
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
|
||||
im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
|
||||
im->ddr.sdram_mode =
|
||||
(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
|
||||
im->ddr.sdram_interval =
|
||||
|
|
@ -160,7 +162,6 @@ long int initdram(int board_type)
|
|||
ddr_enable_ecc(msize * 1048576);
|
||||
#endif
|
||||
|
||||
puts(" DDR RAM: ");
|
||||
/* return total bus RAM size(bytes) */
|
||||
return msize * 1024 * 1024;
|
||||
}
|
||||
|
|
@ -385,22 +386,22 @@ int misc_init_r(void)
|
|||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
@ -31,6 +31,8 @@
|
|||
#include <i2c.h>
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
@ -332,8 +334,40 @@ void pci_init_board(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
#ifdef CONFIG_MPC83XX_PCI2
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
|
||||
tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
|
|
@ -355,3 +389,4 @@ ft_pci_setup(void *blob, bd_t *bd)
|
|||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_FLAT_TREE */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o pci.o
|
||||
COBJS := $(BOARD).o pci.o ../common/pq-mds-pib.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
@ -29,7 +29,9 @@
|
|||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#endif
|
||||
#if defined(CONFIG_PQ_MDS_PIB)
|
||||
#include "../common/pq-mds-pib.h"
|
||||
#endif
|
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
|
|
@ -107,6 +109,14 @@ int board_early_init_f(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_PQ_MDS_PIB
|
||||
pib_init();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
#endif
|
||||
|
|
@ -139,7 +149,7 @@ long int initdram(int board_type)
|
|||
* Initialize SDRAM if it is on local bus.
|
||||
*/
|
||||
sdram_init();
|
||||
puts(" DDR RAM: ");
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -224,8 +234,6 @@ void sdram_init(void)
|
|||
volatile lbus83xx_t *lbc = &immap->lbus;
|
||||
uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
|
||||
|
||||
puts("\n SDRAM on Local Bus: ");
|
||||
print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
|
||||
*/
|
||||
|
|
@ -281,36 +289,13 @@ void sdram_init(void)
|
|||
#else
|
||||
void sdram_init(void)
|
||||
{
|
||||
puts("SDRAM on Local Bus is NOT available!\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
|
||||
&& defined(CONFIG_OF_BOARD_SETUP)
|
||||
|
||||
/*
|
||||
* Prototypes of functions that we use.
|
||||
*/
|
||||
void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void ft_pci_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
int nodeoffset;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/memory");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
||||
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
||||
fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
}
|
||||
#else
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
|
|
@ -320,10 +305,9 @@ ft_board_setup(void *blob, bd_t *bd)
|
|||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
#endif
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif /* CONFIG_OF_x */
|
||||
#endif
|
||||
|
|
@ -22,7 +22,6 @@
|
|||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#endif
|
||||
|
||||
#include <asm/fsl_i2c.h>
|
||||
|
|
@ -132,7 +131,6 @@ void pci_init_board(void)
|
|||
volatile pcictrl83xx_t *pci_ctrl;
|
||||
volatile pciconf83xx_t *pci_conf;
|
||||
|
||||
u8 val8, orig_i2c_bus;
|
||||
u16 reg16;
|
||||
u32 val32;
|
||||
u32 dev;
|
||||
|
|
@ -200,43 +198,6 @@ void pci_init_board(void)
|
|||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
|
||||
PIWAR_IWS_2G;
|
||||
|
||||
/*
|
||||
* Assign PIB PMC slot to desired PCI bus
|
||||
*/
|
||||
|
||||
/* Switch temporarily to I2C bus #2 */
|
||||
orig_i2c_bus = i2c_get_bus_num();
|
||||
i2c_set_bus_num(1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x23, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x23, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x23, 0x2, 1, &val8, 1);
|
||||
i2c_write(0x23, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
||||
val8 = 0x34;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
|
||||
val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */
|
||||
i2c_write(0x26, 0x2, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x26, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x27, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x27, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x27, 0x2, 1, &val8, 1);
|
||||
val8 = 0xef;
|
||||
i2c_write(0x27, 0x3, 1, &val8, 1);
|
||||
asm("eieio");
|
||||
|
||||
/* Reset to original I2C bus */
|
||||
i2c_set_bus_num(orig_i2c_bus);
|
||||
|
||||
/*
|
||||
* Release PCI RST Output signal
|
||||
*/
|
||||
|
|
@ -293,8 +254,6 @@ void pci_init_board(void)
|
|||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
|
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
|
||||
|
||||
printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
|
||||
|
||||
/*
|
||||
* Hose scan.
|
||||
*/
|
||||
|
|
@ -314,7 +273,12 @@ ft_pci_setup(void *blob, bd_t *bd)
|
|||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(hose[0].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
|
|
@ -64,8 +64,6 @@ long int initdram (int board_type)
|
|||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
|
||||
return -1;
|
||||
|
||||
puts("Initializing\n");
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
|
|
@ -84,7 +82,6 @@ long int initdram (int board_type)
|
|||
*/
|
||||
ddr_enable_ecc(msize * 1024 * 1024);
|
||||
#endif
|
||||
puts(" DDR RAM: ");
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
|
@ -130,7 +127,7 @@ int fixed_sdram(void)
|
|||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
| SDRAM_CFG_2T_EN
|
||||
#endif
|
||||
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR1;
|
||||
#if defined (CONFIG_DDR_32BIT)
|
||||
/* for 32-bit mode burst length is 8 */
|
||||
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ long int initdram (int board_type)
|
|||
/* enable DDR controller */
|
||||
im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
|
||||
SDRAM_CFG_SREN |
|
||||
SDRAM_CFG_SDRAM_TYPE_DDR);
|
||||
SDRAM_CFG_SDRAM_TYPE_DDR1);
|
||||
SYNC;
|
||||
|
||||
/* size detection */
|
||||
|
|
@ -388,7 +388,7 @@ static void set_ddr_config(void) {
|
|||
/* don't enable DDR controller yet */
|
||||
im->ddr.sdram_cfg =
|
||||
SDRAM_CFG_SREN |
|
||||
SDRAM_CFG_SDRAM_TYPE_DDR;
|
||||
SDRAM_CFG_SDRAM_TYPE_DDR1;
|
||||
SYNC;
|
||||
|
||||
/* Set SDRAM mode */
|
||||
|
|
|
|||
|
|
@ -35,12 +35,10 @@
|
|||
#include <ft_build.h>
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
int checkcpu(void)
|
||||
{
|
||||
volatile immap_t *immr;
|
||||
|
|
@ -333,9 +331,7 @@ void watchdog_reset (void)
|
|||
*/
|
||||
static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
/*
|
||||
* Fix it up if it exists, don't create it if it doesn't exist.
|
||||
*/
|
||||
/* Fix it up if it exists, don't create it if it doesn't exist */
|
||||
if (fdt_get_property(blob, nodeoffset, name, 0)) {
|
||||
return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
|
||||
}
|
||||
|
|
@ -345,9 +341,7 @@ static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
|||
/* second onboard ethernet port */
|
||||
static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
/*
|
||||
* Fix it up if it exists, don't create it if it doesn't exist.
|
||||
*/
|
||||
/* Fix it up if it exists, don't create it if it doesn't exist */
|
||||
if (fdt_get_property(blob, nodeoffset, name, 0)) {
|
||||
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
|
||||
}
|
||||
|
|
@ -358,9 +352,7 @@ static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
|||
/* third onboard ethernet port */
|
||||
static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
/*
|
||||
* Fix it up if it exists, don't create it if it doesn't exist.
|
||||
*/
|
||||
/* Fix it up if it exists, don't create it if it doesn't exist */
|
||||
if (fdt_get_property(blob, nodeoffset, name, 0)) {
|
||||
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
|
||||
}
|
||||
|
|
@ -371,9 +363,7 @@ static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
|||
/* fourth onboard ethernet port */
|
||||
static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
/*
|
||||
* Fix it up if it exists, don't create it if it doesn't exist.
|
||||
*/
|
||||
/* Fix it up if it exists, don't create it if it doesn't exist */
|
||||
if (fdt_get_property(blob, nodeoffset, name, 0)) {
|
||||
return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
|
||||
}
|
||||
|
|
@ -384,9 +374,7 @@ static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
|||
static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
/*
|
||||
* Create or update the property.
|
||||
*/
|
||||
/* Create or update the property */
|
||||
tmp = cpu_to_be32(bd->bi_busfreq);
|
||||
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
|
@ -394,14 +382,38 @@ static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *b
|
|||
static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
/*
|
||||
* Create or update the property.
|
||||
*/
|
||||
/* Create or update the property */
|
||||
tmp = cpu_to_be32(OF_TBCLK);
|
||||
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
|
||||
static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
/* Create or update the property */
|
||||
tmp = cpu_to_be32(gd->core_clk);
|
||||
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_QE
|
||||
static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
/* Create or update the property */
|
||||
tmp = cpu_to_be32(gd->qe_clk);
|
||||
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
/* Create or update the property */
|
||||
tmp = cpu_to_be32(gd->brg_clk);
|
||||
return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Fixups to the fdt.
|
||||
*/
|
||||
|
|
@ -420,6 +432,10 @@ static const struct {
|
|||
},
|
||||
{ "/cpus/" OF_CPU,
|
||||
"clock-frequency",
|
||||
fdt_set_clockfreq
|
||||
},
|
||||
{ "/" OF_SOC,
|
||||
"bus-frequency",
|
||||
fdt_set_busfreq
|
||||
},
|
||||
{ "/" OF_SOC "/serial@4500",
|
||||
|
|
@ -450,6 +466,15 @@ static const struct {
|
|||
fdt_set_eth1
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_QE
|
||||
{ "/" OF_QE,
|
||||
"brg-frequency",
|
||||
fdt_set_qe_brgfreq
|
||||
},
|
||||
{ "/" OF_QE,
|
||||
"bus-frequency",
|
||||
fdt_set_qe_busfreq
|
||||
},
|
||||
#ifdef CONFIG_UEC_ETH1
|
||||
#if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
|
||||
{ "/" OF_QE "/ucc@2000",
|
||||
|
|
@ -481,7 +506,7 @@ static const struct {
|
|||
"local-mac-address",
|
||||
fdt_set_eth1
|
||||
},
|
||||
#elif CFG_UEC1_UCC_NUM == 3 /* UCC4 */
|
||||
#elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
|
||||
{ "/" OF_QE "/ucc@3200",
|
||||
"mac-address",
|
||||
fdt_set_eth1
|
||||
|
|
@ -492,14 +517,16 @@ static const struct {
|
|||
},
|
||||
#endif
|
||||
#endif /* CONFIG_UEC_ETH2 */
|
||||
#endif /* CONFIG_QE */
|
||||
};
|
||||
|
||||
void
|
||||
ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int j;
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int j;
|
||||
int tmp[2];
|
||||
|
||||
for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
|
||||
nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node);
|
||||
|
|
@ -508,15 +535,29 @@ ft_cpu_setup(void *blob, bd_t *bd)
|
|||
fixup_props[j].prop, bd);
|
||||
if (err < 0)
|
||||
debug("Problem setting %s = %s: %s\n",
|
||||
fixup_props[j].node,
|
||||
fixup_props[j].prop,
|
||||
fdt_strerror(err));
|
||||
fixup_props[j].node, fixup_props[j].prop,
|
||||
fdt_strerror(err));
|
||||
} else {
|
||||
debug("Couldn't find %s: %s\n",
|
||||
fixup_props[j].node,
|
||||
fdt_strerror(nodeoffset));
|
||||
fixup_props[j].node, fdt_strerror(nodeoffset));
|
||||
}
|
||||
}
|
||||
|
||||
/* update, or add and update /memory node */
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/memory");
|
||||
if (nodeoffset < 0) {
|
||||
nodeoffset = fdt_add_subnode(blob, 0, "memory");
|
||||
if (nodeoffset < 0)
|
||||
debug("failed to add /memory node: %s\n",
|
||||
fdt_strerror(nodeoffset));
|
||||
}
|
||||
if (nodeoffset >= 0) {
|
||||
fdt_setprop(blob, nodeoffset, "device_type",
|
||||
"memory", sizeof("memory"));
|
||||
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
||||
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
||||
fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
}
|
||||
}
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
void
|
||||
|
|
|
|||
|
|
@ -28,7 +28,6 @@
|
|||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#endif
|
||||
|
|
@ -184,7 +183,12 @@ void ft_pci_setup(void *blob, bd_t *bd)
|
|||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
|
||||
if (pci_num_buses < 2)
|
||||
|
|
@ -194,7 +198,12 @@ void ft_pci_setup(void *blob, bd_t *bd)
|
|||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range",
|
||||
tmp, sizeof(tmp));
|
||||
|
||||
tmp[0] = cpu_to_be32(gd->pci_clk);
|
||||
err = fdt_setprop(blob, nodeoffset, "clock-frequency",
|
||||
tmp, sizeof(tmp[0]));
|
||||
}
|
||||
}
|
||||
#elif CONFIG_OF_FLAT_TREE
|
||||
|
|
|
|||
|
|
@ -34,6 +34,30 @@
|
|||
#include <asm/mmu.h>
|
||||
#include <spd_sdram.h>
|
||||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ddr83xx_t *ddr = &immap->ddr;
|
||||
|
||||
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
|
||||
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
|
||||
|
||||
if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
|
||||
puts(", 32-bit");
|
||||
else
|
||||
puts(", 64-bit");
|
||||
|
||||
if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
|
||||
puts(", ECC on)");
|
||||
else
|
||||
puts(", ECC off)");
|
||||
|
||||
#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
|
||||
puts("\nSDRAM: ");
|
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPD_EEPROM
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
@ -109,7 +133,7 @@ long int spd_sdram()
|
|||
unsigned int n_ranks;
|
||||
unsigned int odt_rd_cfg, odt_wr_cfg;
|
||||
unsigned char twr_clk, twtr_clk;
|
||||
unsigned char sdram_type;
|
||||
unsigned int sdram_type;
|
||||
unsigned int memsize;
|
||||
unsigned int law_size;
|
||||
unsigned char caslat, caslat_ctrl;
|
||||
|
|
@ -137,7 +161,7 @@ long int spd_sdram()
|
|||
#endif
|
||||
/* Check the memory type */
|
||||
if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
|
||||
printf("DDR: Module mem type is %02X\n", spd.mem_type);
|
||||
debug("DDR: Module mem type is %02X\n", spd.mem_type);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -578,17 +602,17 @@ long int spd_sdram()
|
|||
burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
|
||||
else
|
||||
burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
|
||||
printf("\n DDR DIMM: data bus width is 32 bit");
|
||||
debug("\n DDR DIMM: data bus width is 32 bit");
|
||||
} else {
|
||||
burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
|
||||
printf("\n DDR DIMM: data bus width is 64 bit");
|
||||
debug("\n DDR DIMM: data bus width is 64 bit");
|
||||
}
|
||||
|
||||
/* Is this an ECC DDR chip? */
|
||||
if (spd.config == 0x02)
|
||||
printf(" with ECC\n");
|
||||
debug(" with ECC\n");
|
||||
else
|
||||
printf(" without ECC\n");
|
||||
debug(" without ECC\n");
|
||||
|
||||
/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
|
||||
Burst type is sequential
|
||||
|
|
@ -718,26 +742,26 @@ long int spd_sdram()
|
|||
* sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
|
||||
*/
|
||||
if (spd.mem_type == SPD_MEMTYPE_DDR)
|
||||
sdram_type = 2;
|
||||
sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
|
||||
else
|
||||
sdram_type = 3;
|
||||
sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
|
||||
|
||||
sdram_cfg = (0
|
||||
| (1 << 31) /* DDR enable */
|
||||
| (1 << 30) /* Self refresh */
|
||||
| (sdram_type << 24) /* SDRAM type */
|
||||
| SDRAM_CFG_MEM_EN /* DDR enable */
|
||||
| SDRAM_CFG_SREN /* Self refresh */
|
||||
| sdram_type /* SDRAM type */
|
||||
);
|
||||
|
||||
/* sdram_cfg[3] = RD_EN - registered DIMM enable */
|
||||
if (spd.mod_attr & 0x02)
|
||||
sdram_cfg |= 0x10000000;
|
||||
sdram_cfg |= SDRAM_CFG_RD_EN;
|
||||
|
||||
/* The DIMM is 32bit width */
|
||||
if (spd.dataw_lsb == 0x20) {
|
||||
if (spd.mem_type == SPD_MEMTYPE_DDR)
|
||||
sdram_cfg |= 0x000C0000;
|
||||
sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
|
||||
if (spd.mem_type == SPD_MEMTYPE_DDR2)
|
||||
sdram_cfg |= 0x00080000;
|
||||
sdram_cfg |= SDRAM_CFG_32_BE;
|
||||
}
|
||||
|
||||
ddrc_ecc_enable = 0;
|
||||
|
|
@ -758,7 +782,7 @@ long int spd_sdram()
|
|||
debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
|
||||
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
|
||||
#endif
|
||||
printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
|
||||
debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
|
||||
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -351,6 +351,7 @@ int get_clocks(void)
|
|||
gd->qe_clk = qe_clk;
|
||||
gd->brg_clk = brg_clk;
|
||||
#endif
|
||||
gd->pci_clk = pci_sync_in;
|
||||
gd->cpu_clk = gd->core_clk;
|
||||
gd->bus_clk = gd->csb_clk;
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -434,6 +434,13 @@ int checkdcache (void);
|
|||
void upmconfig (unsigned int, unsigned int *, unsigned int);
|
||||
ulong get_tbclk (void);
|
||||
void reset_cpu (ulong addr);
|
||||
#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
|
||||
void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
#ifdef CONFIG_PCI
|
||||
void ft_pci_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* $(CPU)/serial.c */
|
||||
int serial_init (void);
|
||||
|
|
|
|||
|
|
@ -113,12 +113,12 @@
|
|||
/* 0x03200064 */
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
|
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_2T_EN \
|
||||
| SDRAM_CFG_DBW_32 )
|
||||
#else
|
||||
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
|
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
|
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE )
|
||||
/* 0x43080000 */
|
||||
#endif
|
||||
|
|
@ -228,7 +228,7 @@
|
|||
#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@
|
|||
#define CONFIG_MPC83XX 1 /* MPC83xx family */
|
||||
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
|
||||
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
|
||||
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
|
||||
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
|
||||
|
||||
/*
|
||||
* System Clock Setup
|
||||
|
|
@ -87,6 +89,7 @@
|
|||
#define CFG_SICRL 0x00000000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
|
|
@ -315,7 +318,7 @@
|
|||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
|
|
|
|||
|
|
@ -339,7 +339,7 @@
|
|||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
|
|
|
|||
|
|
@ -296,7 +296,7 @@ boards, we say we have two, but don't display a message if we find only one. */
|
|||
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_FLAT_TREE
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
/* maximum size of the flat tree (8K) */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@
|
|||
#define CONFIG_MPC83XX 1 /* MPC83XX family */
|
||||
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
|
||||
#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
|
||||
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
|
||||
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
|
||||
|
||||
/*
|
||||
* System Clock Setup
|
||||
|
|
@ -88,6 +90,7 @@
|
|||
#define CFG_SICRL 0x40000000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
|
||||
/*
|
||||
* IMMR new address
|
||||
|
|
@ -309,13 +312,13 @@
|
|||
/*
|
||||
* CS4 on Local Bus, to PIB
|
||||
*/
|
||||
#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
|
||||
#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
|
||||
#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
|
||||
|
||||
/*
|
||||
* CS5 on Local Bus, to PIB
|
||||
*/
|
||||
#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
|
||||
#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
|
||||
#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -705,8 +705,9 @@
|
|||
#define SDRAM_CFG_SREN 0x40000000
|
||||
#define SDRAM_CFG_ECC_EN 0x20000000
|
||||
#define SDRAM_CFG_RD_EN 0x10000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE 0x03000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
|
||||
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
|
||||
#define SDRAM_CFG_DYN_PWR 0x00200000
|
||||
#define SDRAM_CFG_32_BE 0x00080000
|
||||
|
|
|
|||
Loading…
Reference in a new issue