Fman microcode is executable code (AFAICT) loaded into a
coprocessor. As such, if verified boot is enabled, it must be verified
like other executable code. However, this is not currently done.
This commit adds verified boot functionality by encapsulating the
microcode in a FIT, which can then be signed/verified as normal. By
default we allow fallback to unencapsulated firmware, but if
CONFIG_FIT_SIGNATURE is enabled, then we make it mandatory. Because
existing Layerscape do not use this config (instead enabling
CONFIG_CHAIN_OF_TRUST), this should not break any existing boards.
An example (mildly-abbreviated) its is provided below:
/ {
#address-cells = <1>;
images {
firmware {
data = /incbin/(/path/to/firmware);
type = "firmware";
arch = "arm64";
compression = "none";
signature {
algo = "sha256,rsa2048";
key-name-hint = "your key name";
};
};
};
configurations {
default = "conf";
conf {
description = "Load FMAN microcode";
fman = "firmware";
};
};
};
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Several ethernet drivers load firmware from FIT images. Convert them to
use the fit_get_data helpers.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
If ethernet connected to SFP, like this:
&enetc_port0 {
phy-connection-type = "sgmii";
sfp = <&sfp0>;
managed = "in-band-status";
status = "okay";
};
Then enetc_config_phy returns -ENODEV and the memory containing the mdio interface is freed.
It's better to unregister and free mdio resources.
Signed-off-by: Siarhei Yasinski <siarhei.yasinski@sintecs.eu>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The deadline for DM_ETH migration passed 2 years ago. Now that
platforms which cannot be migrated have been either removed or had
drivers disabled, and platforms that needed minor help to migrate have
been forcefully migrated, we can complete the migration.
This entails select'ing DM_ETH under NETDEVICES, and then removing now
extraneous depends on lines. In a few places, we can now either remove
options or just simplify later dependencies.
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
As this driver has been converted to DM_ETH and the migration deadline
is 2 years passed, remove the legacy code and callers.
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
When using DM_ETH, which should be the default now, we need to always
have DM_MDIO and FSL_LS_MDIO enabled, so select them.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Wasim Khan <wasim.khan@nxp.com>
Cc: Udit Agarwal <udit.agarwal@nxp.com>
Cc: Ashish Kumar <Ashish.Kumar@nxp.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Manish Tomar <Manish.Tomar@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This driver has not been converted to DM_ETH. The migration
deadline passed 2 years ago.
Cc: Trevor Woerner <twoerner@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
This driver has not been converted to DM_ETH. The migration deadline
passed 2 years ago.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Liviu Dudau <liviu.dudau@foss.arm.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Ramon Fried <rfried.dev@gmail.com>
This converts the following to Kconfig:
CONFIG_FSL_NGPIXIS
CONFIG_SYS_FSL_QMAN_V3
CONFIG_SYS_FSL_RAID_ENGINE
CONFIG_SYS_FSL_RMU
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
CONFIG_SYS_FSL_SRIO_LIODN
CONFIG_SYS_FSL_TBCLK_DIV
CONFIG_SYS_FSL_USB1_PHY_ENABLE
CONFIG_SYS_FSL_USB2_PHY_ENABLE
CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Signed-off-by: Tom Rini <trini@konsulko.com>
This allows you to specify the type of rgmii-id that will enable phy
internal delay in ethernet phy-mode.
This adds all RGMII cases to all of get_pinmode() except LD11, because LD11
SoC doesn't support RGMII due to the constraint of the hardware. When RGMII
phy mode is specified in the devicetree for LD11, the driver will abort
with an error.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
We check if phydev is NULL. Only but if it is non-NULL we set one
component of phydev. But even if it is NULL we set another. We should not
dereference NULL in either case.
Fixes: e24b58f5ed ("net: phy: don't require PHY interface mode during PHY creation")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reorder include files in the U-Boot expected order.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The convinience functions are not that small and they caused
bloated text segments because of their usage.
There was no need to inline them in the first place, as
they're not part of a fastpath.
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Previously we'd been using a device name retrieved via
ftgmac100_data->phydev, but the mdio read/write functions may be
called before that member is initialized in ftgmac100_phy_init(),
leading to a NULL pointer dereference while printing the error message
issued if the mdio access fails. We can instead use bus->name, which
is already available at that point.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: 538e75d3fc ("net: ftgmac100: add MDIO bus and phylib support")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
NPCM750 provides identical ethernet MAC controllers for WAN/LAN applications.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Only two boards in the tree set the macro DWC_NET_PHYADDR. Both have
CONFIG_DM_ETH_PHY=y, so should set the phy address in DT if necessary.
The imx8mp_evk does set the correct address in device tree.
The other board seems to be a copy-paste-adapt from an old
version of the imx8mp_evk config header, given the "#ifdef
CONFIG_DWC_ETH_QOS" block that has been removed from imx8mp_evk header
in commit 127fb45495. Its device tree doesn't even enable (i.e., set
'status = "okay"') the &eqos node. But the other ethernet device,
&fec, does get enabled, and does have a phy sitting at address 4 (and
it also has a corresponding legacy #define CONFIG_FEC_MXC_PHYADDR
4). So I believe it should be completely safe to remove it from there
as well.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
[trini: Re-apply to top of tree, update imx93_evk.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
I have an iMX8MP with a ti,dp83867 phy in front of the eqos
interface. The phy is Gbit capable - however, the C and D differential
pairs are not physically routed to the RJ45 connector. So I need to
prevent the phy from advertising 1000Mbps.
The necessary code is almost already there in the form of a
phy_set_supported() call in eqos_start(), but the max-speed DT
property is currently only parsed in
eqos_probe_resources_stm32(). Lift that parsing to eqos_probe().
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Not only does eqos_remove() fail to free the buffers that have been
allocated by eqos_probe_resources_core(), it repeats those allocations
and thus drops twice as much memory on the floor.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Assign packet pointer only in case the MAC reports anything in the FIFO.
In case the MAC indicates empty FIFO, return 0 to pass that information
to the network stack.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This patch adds basic support for the Marvell 88E1240 PHY.
This will be used by the upcoming ethernet support addition for the
Marvell MIPS Octeon EBB7304 platform.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
This patch adds support for the "marvell,reg-init" DT property, which
is used to describe board specific Marvell PHY register configurations
in the board dts file. This DT property is supported in the Linux Kernel
since a longer time. Adding it to U-Boot now, enables the boards which
describe the register settings in their DT files here as well.
I've included calling this marvell_of_reg_init() to all foo_config()
functions in this patch as well. If CONFIG_DM_ETH is not set, there is
no ofnode, or no "marvell,reg-init" property, the PHY initialization is
unchanged.
The function marvell_of_reg_init() is a port of the Linux version.
Please note that I explicitly did not add error checking and handling
to the U-Boot version, as this is basically not done for phy_read/write
in this Marvell PHY code.
This will be used by the upcoming ethernet support on the MIPS
Octeon EBB 7304 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Since new atheros PHY driver needs to access its PHY node through
phy device, we have to assign the phy node in ethernet controller
driver. Otherwise the PHY driver will fail to get some nodes
and properties.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move i.MX code to a standalone file to make it easy for adding new
platform support
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Move macros and structures to header file and make some functions
public, so that could used by other files, this is to
prepare split platform specific config to one file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
When CONFIG_CLK is not enabled, there will be buil break:
"error: ‘eqos’ undeclared (first use in this function)"
Take eqos definition out the CONFIG_CLK ifdef.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This header is not used since commit abdbefba2a ("net: sun8i_emac: Use
consistent clock bitfield definitions"). Dropping it allows the driver
to be architecture-independent.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This just prints the PHY mode taken from the devicetree. It does not
need to be printed during every boot, and also avoids an unwanted
line break for the "net: " reporting line.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This patch adds GMAC support for MediaTek MT7621 SoC.
MT7621 has the same GMAC/Switch configuration as MT7623.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The address returned by regmap_get_range() is not remapped. Directly r/w
to this address is ok for ARM platforms since it's idential to the virtual
address.
But for MIPS platform only virtual address should be used for access.
To solve this issue, the regmap api regmap_read/regmap_write should be used
since they will remap address before accessing.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The iobase address from dts node is actually physical address. It's
identical to the virtual address in ARM platform. This is ok because this
driver was used only by ARM platforms (mt7622/mt7623 ...).
But now this driver will be used by mt7621 which is a MIPS SoC. For MIPS
platform the physical address space is mapped to KSEG0 and KSEG1 and this
makes the virtual address apparently not idential to its physical address.
To solve this issue, this patch replaces dev_read_addr with dev_remap_addr
to get the remapped iobase address.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This value is always used at the default, rename it for now. This
likely should come from the device tree if non-default, moving forward.
Signed-off-by: Tom Rini <trini@konsulko.com>
cpu:
- Add driver for microblaze cpu
net:
- Add support for DM_ETH_PHY to AXI emac and emaclite
xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS
zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize
versal:
- Enable loading app at EL1
serial:
- Setup default address and clock rates for DEBUG uarts
pinctrl:
- Add support for tri state and output enable properties
relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze
microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support
timer:
- Extract axi timer driver from Microblaze to generic location
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Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2022.10
cpu:
- Add driver for microblaze cpu
net:
- Add support for DM_ETH_PHY to AXI emac and emaclite
xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS
zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize
versal:
- Enable loading app at EL1
serial:
- Setup default address and clock rates for DEBUG uarts
pinctrl:
- Add support for tri state and output enable properties
relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze
microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support
timer:
- Extract axi timer driver from Microblaze to generic location
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/93e11ccca56b6e52b2dcc283d08d5042537f828f.1652181968.git.michal.simek@amd.com
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/ecfec78234233fefdc172c141c207b2d78ef70c5.1652181968.git.michal.simek@amd.com
Replace reference to the correct name STMicroelectronics
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The ADIN1300 supports generating certain clocks on its GP_CLK pin, as
well as providing the reference clock on CLK25_REF.
Add support for selecting the clock via device-tree properties.
This patch is based on the Linux implementation for this feature,
which has been added to netdev/net-next.git [1].
[2] https://patchwork.kernel.org/project/netdevbpf/cover/20220517085143.3749-1-josua@solid-run.com/
Signed-off-by: Josua Mayer <josua@solid-run.com>
Currently, the adin driver fails to compile.
The original patch introducing the adin driver used the function
phy_get_interface_by_name to support the adi,phy-mode-override
property. Unfortunately, a few days before the adin patch
was accepted, another patch removed support for phy_get_interface_by_name:
123ca114e0
This patch refactors adin_get_phy_mode_override, implementing the logic in
the new function, ofnode_read_phy_mode, from the patch above.
Signed-off-by: Nate Drude <nate.d@variscite.com>
Tested-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
