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net: sun8i_emac: Use consistent clock bitfield definitions

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While the R40 uses a different register for EMAC clock configuration
than other chips, the register has a very similar layout. Reuse the
existing bitfield definitions in this file, since they match.

This allows the driver to compile on the H6 platform, where the
CCM_GMAC_CTRL definitions are not present.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Samuel Holland 2020-05-07 18:10:50 -05:00 • committed by Jagan Teki
parent 5cfeeacaea
commit abdbefba2a
1 changed files with 3 additions and 3 deletions
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6
drivers/net/sun8i_emac.c
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@ -300,9 +300,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
if (priv->variant == R40_GMAC) {
/* Select RGMII for R40 */
reg = readl(priv->sysctl_reg + 0x164);
reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII |
CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
reg |= SC_ETCS_INT_GMII |
SC_EPIT |
(CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
writel(reg, priv->sysctl_reg + 0x164);
return 0;