Commit graph

50903 commits

Author SHA1 Message Date
Bin Meng
252d41f1ae x86: baytrail: Drop EFI-specific test logics
Now that we have generic EFI payload support, drop EFI-specific test
logics in BayTrail Kconfig and codes, and all BayTrail boards too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
93c7b879c7 x86: Drop QEMU-specific EFI payload support
Now that we have generic EFI payload support for all x86 boards,
drop the QEMU-specific one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
32151d4017 x86: Add generic EFI payload support
It is possible to create a generic EFI payload for all x86 boards.
The payload is configured to include as many generic drivers as
possible. All stuff that touches low-level initialization are not
allowed as such is the EFI BIOS's responsibility. Platform specific
drivers (like gpio, spi, etc) are not included.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
3773c6a20a x86: efi: payload: Add arch_cpu_init()
This adds arch_cpu_init() to the payload codes, in preparation for
supporting a generic efi payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
4f1dacd43f x86: efi: Refactor the directory of EFI app and payload support
At present the EFI application and payload support codes in the x86
directory is distributed in a hybrid way. For example, the Kconfig
options for both app and payload are in arch/x86/lib/efi/Kconfig,
but the source codes in the same directory get built only for
CONFIG_EFI_STUB.

This refactors the codes by consolidating all the EFI support codes
into arch/x86/cpu/efi, just like other x86 targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
9efeb3f4db x86: doc: Fix reference to EFI doc in U-Boot
Since commit f3b5056c4e ("efi_loader: split README.efi into two
separate documents"), the original README.efi was renamed to
README.u-boot_on_efi, but x86 doc still refers to the old one.

This updates the x86 doc to reference both README.u-boot_on_efi and
README.uefi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-17 21:16:04 +08:00
Ivan Gorinov
9f0b0113c9 x86: use EFI calling convention for efi_main on x86_64
UEFI specifies the calling convention used in Microsoft compilers;
first arguments of a function are passed in (%rcx, %rdx, %r8, %r9).

All other compilers use System V ABI by default, passing first integer
arguments of a function in (%rdi, %rsi, %rdx, %rcx, %r8, %r9).

These ABI also specify different sets of registers that must be preserved
across function calls (callee-saved).

GCC allows using the Microsoft calling convention by adding the ms_abi
attribute to a function declaration.

Current EFI implementation in U-Boot specifies EFIAPI for efi_main()
in the test apps but uses default calling convention in lib/efi.

Save efi_main() arguments in the startup code on x86_64;
use EFI calling convention for _relocate() on x86_64;
consistently use EFI calling convention for efi_main() everywhere.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-17 21:16:04 +08:00
Bin Meng
e3ec0d03bb x86: cherryhill: Fix DTC warning
Fix warning when compiling cherryhill.dts with latest DTC:

  "Warning (avoid_unnecessary_addr_size): /pci/pch@1f,0: unnecessary
   #address-cells/#size-cells without "ranges" or child "reg" property"

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Tom Rini
103c45fb0d Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-17 09:09:40 -04:00
Tom Rini
a715415bb5 Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-06-16 00:07:37 -04:00
Marek Vasut
891bf67611 ARM: rmobile: Disable 4k SF sectors on V3M Eagle
The V3M Eagle uses flash with 128 kiB or 256 kiB sectors,
disable the 4k sector support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 04:27:28 +02:00
Marek Vasut
75b573fe23 ARM: rmobile: Enable cache command on V3M Eagle
Turning the cache off can help when experimenting with bare metal
applications, enable the cache command on V3M Eagle to make that
easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 04:27:28 +02:00
Marek Vasut
c267952c41 ARM: rmobile: Fix CPGW address on V3M Eagle
Fix the CPGWPR/CPGWPCR register address on V3M Eagle to unlock
access to the CPG clock control registers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 04:27:28 +02:00
Marek Vasut
6d82ed8d37 ARM: dts: rmobile: Add AVB PHY reset on V3M Eagle
Add EtherAVB PHY reset on V3M Eagle to let the AVB driver unreset the PHY.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 04:27:28 +02:00
Marek Vasut
29904b923e ARM: dts: rmobile: Add AVB pinmux on V3M Eagle
Add EtherAVB pinmux node on V3M Eagle to set the pinmux configuration.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 04:27:28 +02:00
Marek Vasut
bc19d28e6d ARM: dts: rmobile: Enable SDHI on E3 Ebisu
Enable SDHI on R8A77990 E3 Ebisu in DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 02:17:57 +02:00
Marek Vasut
ef6765ca62 ARM: dts: rmobile: Add initial SDHI nodes to R8A77990 E3
Add SDHI nodes to R8A77990 E3 SoC to allow SDHI operation.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 02:17:57 +02:00
Marek Vasut
65dcc809cd ARM: dts: rmobile: Add SCIF2 pinmux to E3 Ebisu
Add SCIF2 pinmux nodes to R8A77990 E3 Ebisu.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 02:17:57 +02:00
Marek Vasut
e183a6c7f2 ARM: dts: rmobile: Add Renesas RPC HF/QSPI DT node to R8A77990
Add device tree nodes for the Renesas RPC HF/QSPI controller
to R8A77990 E3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 02:17:57 +02:00
Marek Vasut
c599de372f ARM: rmobile: Enable RPCHF on Draak
Enable the Renesas RPC HF driver on R8A77995 D3 Draak.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-16 02:17:57 +02:00
Marek Vasut
b08a704ddc ARM: rmobile: Fix environment placement on Draak
The environment on Draak is in the eMMC, card 0, place it so.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-06-16 02:17:57 +02:00
Tom Rini
f58e779513 Merge tag 'arc-updates-for-2018.07-rc2' of git://git.denx.de/u-boot-arc
Here we just add a tool for HSDK flashable images preparation
together with extensive documentation for HSDK board.

This will help real-life users to update U-Boot on the board.
2018-06-15 09:38:16 -04:00
Tom Rini
d94e89c765 Xilinx fixes for v2018.07-rc2
Zynq:
 - Fix missing watchdog header
 - DT fixes
 
 ZynqMP:
 - emmc configuration split
 - Enable SPD
 - Fix PMUFW_INIT_FILE logic
 - Coverity fixes in SoC code
 
 timer
 - Add timer_get_boot_us
 
 mmc:
 - Fix MMC HS200 tuning command
 
 serial:
 - Fix scrabled chars with OF_LIVE
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Merge tag 'xilinx-for-v2018.07-rc2' of git://git.denx.de/u-boot-microblaze

Xilinx fixes for v2018.07-rc2

Zynq:
- Fix missing watchdog header
- DT fixes

ZynqMP:
- emmc configuration split
- Enable SPD
- Fix PMUFW_INIT_FILE logic
- Coverity fixes in SoC code

timer
- Add timer_get_boot_us

mmc:
- Fix MMC HS200 tuning command

serial:
- Fix scrabled chars with OF_LIVE
2018-06-15 09:38:06 -04:00
Alexey Brodkin
3b4410dde3 ARC: HSDK: Add readme
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-06-15 15:54:43 +03:00
Eugeniy Paltsev
9ddcfef6d4 ARC: HSDK: Add tool and make target to generate bsp
HSDK board has preloader that reads SPI flash pages and searches
for a special image header to fetch and load binary.

Add tool, make target (bsp-generate) to generate
update script and u-boot binary image with header for preloader.

Also add script to default environment to apply updates.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-06-15 15:54:43 +03:00
Michal Simek
b729ed0d95 serial: zynq: Make zynq_serial_setbrg static
This function is used only inside this driver that's why should be
static.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
a673025535 serial: zynq: Initialize uart only before relocation
This issue was found when OF_LIVE was enabled that there are scrambled
chars on the console like this:
Chip ID:	zu3eg
Watchdog: Started��j�   sdhci@ff160000: 0, sdhci@ff170000: 1
In:    serial@ff010000

I found a solution for this problem exactly the same as I found later in
serial_msm fixed by:
"serial: serial_msm: initialize uart only before relocation"
(sha1: 7e5ad796bc)

What it is happening is that output TX fifo still contains chars to be
sent and _uart_zynq_serial_init() resets TX fifo even in the middle of
transfer.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
e90d2659e4 serial: zynq: Write chars till output fifo is full
Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
c9a2c47b91 serial: zynq: Use BIT macros instead of shifts and full hex numbers
Coding style is checking to use BIT macros instead of shifts.
The patch is also fixing the rest of macros which should be BITs instead
of hex numbers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
01fcf01e81 gpio: zynq_gpio: bank description should use unsigned type
Use u32 instead of int for max_bank, bank_min and bank_max. These values
can't be negative that's why no reason to use signed type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:05 +02:00
Michal Simek
e3c26b8d95 arm64: zynqmp: Check return value in zynqmp_mmio_rawwrite()
There should be return value check from zynqmp_mmio_read() in
zynqmp_mmio_rawwrite() to make sure that errors are propagated properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:05 +02:00
Michal Simek
1e3e68f109 arm64: zynqmp: Check return value from calloc
calloc() can fail and return NULL. The patch is checking return value
and return in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:05 +02:00
Michal Simek
b6911780b5 mmc: zynq: Fix tuning_loop_counter type in arasan_sdhci_execute_tuning()
Code around tuning_loop_counter variable expects to go below zero.
That's why this variable can't use unsigned type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:04 +02:00
Michal Simek
1471fadf69 gpio: zynq: Do not check unsigned type that is >= 0
There is no reason to check that unsigned type that is >= 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:04 +02:00
Siva Durga Prasad Paladugu
1a7414f626 mmc: sdhci: Fix MMC HS200 tuning command failures
This patch fixes the mmc tuning command failures
when tuning pattern data needs to read back for
comparision against the expected bit pattern.

Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-15 08:54:04 +02:00
Luca Ceresoli
c7df098a71 arm64: zynqmp: accept an absolute path for PMUFW_INIT_FILE
The value of PMUFW_INIT_FILE is prefixed with "$(srctree)/", thus
forcing it to be a relative path inside the U-Boot source tree. Since
the PMUFW is a binary file generated outside of U-Boot, the PMUFW
binary must be copied inside the U-Boot source tree before the
build.

This generates a few problems:

 * if the source tree is shared among different out-of-tree builds,
   they will pollute (and potentially corrupt) each other
 * the source tree cannot be read-only
 * any buildsystem must add a command to copy the PMUFW binary
 * putting an externally-generated binary in the source tree is ugly
   as hell

Avoid these problems by accepting an absolute path for
PMUFW_INIT_FILE. This would be as simple as removing the "$(srctree)/"
prefix, but in order to keep backward compatibility we rather use the
shell and readlink to get the absolute path even when starting from a
relative path.

Since 'readlink -f' produces an empty string if the file does not
exist, we also add a check to ensure the file configured in
PMUFW_INIT_FILE exists. Otherwise the build would exit successfully,
but produce a boot.bin without PMUFW as if PMUFW_INIT_FILE were empty.

Tested in the 12 possible combinations of:
 - PMUFW_INIT_FILE empty, relative, absolute, non-existing
 - building in-tree, in subdir, in other directory

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Emmanuel Vadot <manu@bidouilliste.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:04 +02:00
Michal Simek
343671e483 arm64: zynqmp: Enable SPD ddr support for zcu102 targets
zcu102 contains DIMM with SPD on it at 0x51 address.
For example:
i2c dev 13
i2c sdram 51

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Michal Simek
56c0e646c4 timer: cadence: Implement timer_get_boot_us
This function is required for adding bootstage support.
Also enable it directly for ZynqMP R5 configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Michal Simek
3c1eaec012 arm: zynq: Drop #address-cells and #size-cells from gpio-keys
dtc is showing some warnings and this change was also done in
the Linux kernel as "Input: gpio-keys - clean up device tree binding
example"
with this fragment in commit message
"Drop #address-cells and #size-cells, which are not required by the
gpio-keys binding documentation, as button sub-nodes are not devices."

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Siva Durga Prasad Paladugu
bc0f4ed133 arm64: zynqmp: Split emmc configuration into emmc0 and emmc1
This patch splits the current mini emmc configuration into emmc0
and emmc1 configurations because emmc is probed at boot time and on
systems which have only one interface mini configuration is failing on
unused interface. This patch also adds required clock node in dts and
enables CONFIG_MMC_SDHCI_ZYNQ through defconfig.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Michal Simek
0ecd14e636 arm: zynq: Add missing watchdog header
Add missing header detected by sparse.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Marek Vasut
4b334b6054 ARM: rmobile: Point load address to more sane area on Gen3
Point the $loadaddr variable and default load address to a more sane
area, 384 MiB from the start of RAM. This is to avoid all the reserved
memory at the beginning of RAM. The old behavior could still be easily
retained by "setenv loadaddr 0x48080000" . The new setup allows us to
use for example modern fitImage with kernel_noload, so use this as a
new preferred default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
910db6c3a1 ARM: rmobile: Point load address to more sane area on Gen2
Point the $loadaddr variable and default load address to a more sane
area, 256 MiB from the start of RAM. While it is convenient to use
uImage without copying, which is why the previous load address was
set the way it was, uImage is now legacy. This behavior could still
be easily retained by "setenv loadaddr 0x40007fc0" . The new setup
allows us to use for example modern fitImage with kernel_noload, so
use this as a new preferred default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
c29d2a2432 ARM: rmobile: Zap CONFIG_SYS_CLK_FREQ where applicable
The CONFIG_SYS_CLK_FREQ is not used on some of the Gen3 boards,
remove it. Moreover, on Ebisu this actually didn't match the
comment in the config file at all, but since it was not used,
there was no real problem.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
2519a293d5 ARM: rmobile: Sync Gen3 DTS with Linux v4.17
Sync the DTs with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
252c8b45c9 ARM: rmobile: Sync Gen2 DTS with Linux v4.17
Sync the DTs with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
bf8d2dab38 pinctrl: renesas: Sync Gen3 PFC tables with Linux v4.17
Sync the PFC tables with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Tom Rini
9d0dc69235 Patch queue for efi - 2018-06-14
A few minor fixes for the release:
 
   - Compile fixes
   - HI20 relocations for RISC-V
   - Fix bootefi without load path
   - Fix Runtime Services with certain compilers
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-06-14

A few minor fixes for the release:

  - Compile fixes
  - HI20 relocations for RISC-V
  - Fix bootefi without load path
  - Fix Runtime Services with certain compilers
2018-06-14 13:28:03 -04:00
Marek Vasut
2e975d8628 pinctrl: renesas: Sync Gen2 PFC tables with Linux v4.17
Sync the PFC tables with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Marek Vasut
6995fc3aca clk: rmobile: Add R8A77995 RPC clock
Add missing RPC entry into the R8A77995 clock driver tables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00