mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-17 23:37:01 +00:00
ARM: rmobile: Sync Gen3 DTS with Linux v4.17
Sync the DTs with Linux v4.17. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
parent
252c8b45c9
commit
2519a293d5
9 changed files with 2042 additions and 427 deletions
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@ -27,11 +27,6 @@
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i2c7 = &i2c_dvfs;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -43,6 +38,9 @@
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power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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};
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a57_1: cpu@1 {
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@ -52,6 +50,9 @@
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power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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};
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a57_2: cpu@2 {
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@ -61,6 +62,9 @@
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power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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};
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a57_3: cpu@3 {
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@ -70,6 +74,9 @@
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power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
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operating-points-v2 = <&cluster0_opp>;
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#cooling-cells = <2>;
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};
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a53_0: cpu@100 {
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@ -79,6 +86,8 @@
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power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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};
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a53_1: cpu@101 {
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@ -88,6 +97,8 @@
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power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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};
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a53_2: cpu@102 {
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@ -97,6 +108,8 @@
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power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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};
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a53_3: cpu@103 {
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@ -106,6 +119,8 @@
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power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
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operating-points-v2 = <&cluster1_opp>;
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};
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L2_CA57: cache-controller-0 {
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@ -167,15 +182,99 @@
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clock-frequency = <0>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <830000>;
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clock-latency-ns = <300000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <830000>;
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clock-latency-ns = <300000>;
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};
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opp-1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <830000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp-1600000000 {
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opp-hz = /bits/ 64 <1600000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <300000>;
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turbo-mode;
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};
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opp-1700000000 {
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opp-hz = /bits/ 64 <1700000000>;
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opp-microvolt = <960000>;
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clock-latency-ns = <300000>;
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turbo-mode;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <820000>;
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clock-latency-ns = <300000>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <820000>;
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clock-latency-ns = <300000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <820000>;
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clock-latency-ns = <300000>;
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};
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* External PCIe clock - can be overridden by the board */
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pcie_bus_clk: pcie_bus {
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pmu_a57 {
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compatible = "arm,cortex-a57-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a57_0>,
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<&a57_1>,
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<&a57_2>,
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<&a57_3>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>,
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<&a53_1>,
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<&a53_2>,
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<&a53_3>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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@ -217,7 +316,7 @@
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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@ -232,12 +331,12 @@
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 28>;
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gpio-ranges = <&pfc 0 32 29>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a7795",
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"renesas,gpio-rcar";
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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@ -335,42 +434,6 @@
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resets = <&cpg 905>;
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};
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pmu_a57 {
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compatible = "arm,cortex-a57-pmu";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a57_0>,
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<&a57_1>,
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<&a57_2>,
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<&a57_3>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&a53_0>,
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<&a53_1>,
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<&a53_2>,
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<&a53_3>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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@ -418,6 +481,155 @@
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resets = <&cpg 407>;
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};
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ipmmu_vi0: mmu@febd0000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfebd0000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 14>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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#iommu-cells = <1>;
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};
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ipmmu_vi1: mmu@febe0000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfebe0000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 15>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_vp0: mmu@fe990000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfe990000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 16>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_vp1: mmu@fe980000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfe980000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 17>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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#iommu-cells = <1>;
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};
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ipmmu_vc0: mmu@fe6b0000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfe6b0000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 12>;
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power-domains = <&sysc R8A7795_PD_A3VC>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_vc1: mmu@fe6f0000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfe6f0000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 13>;
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power-domains = <&sysc R8A7795_PD_A3VC>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_pv0: mmu@fd800000 {
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfd800000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 6>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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#iommu-cells = <1>;
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status = "disabled";
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};
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ipmmu_pv1: mmu@fd950000 {
|
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfd950000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 7>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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#iommu-cells = <1>;
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status = "disabled";
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};
|
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ipmmu_pv2: mmu@fd960000 {
|
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xfd960000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 8>;
|
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
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#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_pv3: mmu@fd970000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
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reg = <0 0xfd970000 0 0x1000>;
|
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renesas,ipmmu-main = <&ipmmu_mm 9>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
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#iommu-cells = <1>;
|
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status = "disabled";
|
||||
};
|
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|
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ipmmu_ir: mmu@ff8b0000 {
|
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compatible = "renesas,ipmmu-r8a7795";
|
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reg = <0 0xff8b0000 0 0x1000>;
|
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renesas,ipmmu-main = <&ipmmu_mm 3>;
|
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power-domains = <&sysc R8A7795_PD_A3IR>;
|
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#iommu-cells = <1>;
|
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status = "disabled";
|
||||
};
|
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|
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ipmmu_hc: mmu@e6570000 {
|
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compatible = "renesas,ipmmu-r8a7795";
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reg = <0 0xe6570000 0 0x1000>;
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renesas,ipmmu-main = <&ipmmu_mm 2>;
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
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#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp0: mmu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7795";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
|
@ -450,6 +662,14 @@
|
|||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
||||
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
||||
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
||||
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
|
||||
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
|
||||
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
|
||||
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
|
||||
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
|
@ -484,6 +704,14 @@
|
|||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
|
||||
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
|
||||
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
|
||||
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
|
||||
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
|
@ -518,6 +746,14 @@
|
|||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
|
||||
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
|
||||
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
|
||||
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
|
||||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
|
@ -552,6 +788,14 @@
|
|||
resets = <&cpg 502>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
|
||||
<&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
|
||||
<&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
|
||||
<&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
|
||||
<&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
|
||||
<&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
|
||||
<&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
|
||||
<&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
|
||||
};
|
||||
|
||||
audma1: dma-controller@ec720000 {
|
||||
|
@ -586,6 +830,14 @@
|
|||
resets = <&cpg 501>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
|
||||
<&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
|
||||
<&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
|
||||
<&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
|
||||
<&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
|
||||
<&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
|
||||
<&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
|
||||
<&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
|
@ -627,7 +879,8 @@
|
|||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii-txid";
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
@ -820,8 +1073,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
|
||||
<&dmac2 0x31>, <&dmac2 0x30>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 520>;
|
||||
status = "disabled";
|
||||
|
@ -837,8 +1091,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
|
||||
<&dmac2 0x33>, <&dmac2 0x32>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 519>;
|
||||
status = "disabled";
|
||||
|
@ -854,8 +1109,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
|
||||
<&dmac2 0x35>, <&dmac2 0x34>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 518>;
|
||||
status = "disabled";
|
||||
|
@ -966,8 +1222,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
||||
<&dmac2 0x51>, <&dmac2 0x50>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 207>;
|
||||
status = "disabled";
|
||||
|
@ -982,8 +1239,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
||||
<&dmac2 0x53>, <&dmac2 0x52>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 206>;
|
||||
status = "disabled";
|
||||
|
@ -998,8 +1256,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
|
@ -1046,8 +1305,9 @@
|
|||
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
|
||||
<&dmac2 0x5b>, <&dmac2 0x5a>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 202>;
|
||||
status = "disabled";
|
||||
|
@ -1079,8 +1339,9 @@
|
|||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 931>;
|
||||
dmas = <&dmac1 0x91>, <&dmac1 0x90>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
|
||||
<&dmac2 0x91>, <&dmac2 0x90>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1095,8 +1356,9 @@
|
|||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 930>;
|
||||
dmas = <&dmac1 0x93>, <&dmac1 0x92>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
|
||||
<&dmac2 0x93>, <&dmac2 0x92>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1111,8 +1373,9 @@
|
|||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 929>;
|
||||
dmas = <&dmac1 0x95>, <&dmac1 0x94>;
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
|
||||
<&dmac2 0x95>, <&dmac2 0x94>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -1456,6 +1719,20 @@
|
|||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 815>;
|
||||
status = "disabled";
|
||||
iommus = <&ipmmu_hc 2>;
|
||||
};
|
||||
|
||||
usb3_phy0: usb-phy@e65ee000 {
|
||||
compatible = "renesas,r8a7795-usb3-phy",
|
||||
"renesas,rcar-gen3-usb3-phy";
|
||||
reg = <0 0xe65ee000 0 0x90>;
|
||||
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
|
||||
<&usb_extal_clk>;
|
||||
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 328>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
|
@ -1468,6 +1745,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3_peri0: usb@ee020000 {
|
||||
compatible = "renesas,r8a7795-usb3-peri",
|
||||
"renesas,rcar-gen3-usb3-peri";
|
||||
reg = <0 0xee020000 0 0x400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 328>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 328>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a7795-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
|
@ -1533,7 +1821,8 @@
|
|||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
|
@ -1544,7 +1833,8 @@
|
|||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
|
@ -1555,7 +1845,8 @@
|
|||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
|
@ -1566,7 +1857,8 @@
|
|||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7795";
|
||||
compatible = "renesas,sdhi-r8a7795",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
|
@ -1867,6 +2159,7 @@
|
|||
clocks = <&cpg CPG_MOD 606>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
resets = <&cpg 606>;
|
||||
iommus = <&ipmmu_vp1 7>;
|
||||
};
|
||||
|
||||
fcpf0: fcp@fe950000 {
|
||||
|
@ -1875,6 +2168,7 @@
|
|||
clocks = <&cpg CPG_MOD 615>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
resets = <&cpg 615>;
|
||||
iommus = <&ipmmu_vp0 0>;
|
||||
};
|
||||
|
||||
fcpf1: fcp@fe951000 {
|
||||
|
@ -1883,6 +2177,7 @@
|
|||
clocks = <&cpg CPG_MOD 614>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
resets = <&cpg 614>;
|
||||
iommus = <&ipmmu_vp1 1>;
|
||||
};
|
||||
|
||||
vspbd: vsp@fe960000 {
|
||||
|
@ -1902,6 +2197,7 @@
|
|||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
resets = <&cpg 607>;
|
||||
iommus = <&ipmmu_vp0 5>;
|
||||
};
|
||||
|
||||
vspi0: vsp@fe9a0000 {
|
||||
|
@ -1921,6 +2217,7 @@
|
|||
clocks = <&cpg CPG_MOD 611>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
resets = <&cpg 611>;
|
||||
iommus = <&ipmmu_vp0 8>;
|
||||
};
|
||||
|
||||
vspi1: vsp@fe9b0000 {
|
||||
|
@ -1940,11 +2237,12 @@
|
|||
clocks = <&cpg CPG_MOD 610>;
|
||||
power-domains = <&sysc R8A7795_PD_A3VP>;
|
||||
resets = <&cpg 610>;
|
||||
iommus = <&ipmmu_vp1 9>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x4000>;
|
||||
reg = <0 0xfea20000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
@ -1959,11 +2257,12 @@
|
|||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x4000>;
|
||||
reg = <0 0xfea28000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 622>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
@ -1978,11 +2277,12 @@
|
|||
clocks = <&cpg CPG_MOD 602>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 602>;
|
||||
iommus = <&ipmmu_vi0 9>;
|
||||
};
|
||||
|
||||
vspd2: vsp@fea30000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea30000 0 0x4000>;
|
||||
reg = <0 0xfea30000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 621>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
|
@ -1997,6 +2297,7 @@
|
|||
clocks = <&cpg CPG_MOD 601>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 601>;
|
||||
iommus = <&ipmmu_vi1 10>;
|
||||
};
|
||||
|
||||
fdp1@fe940000 {
|
||||
|
@ -2019,7 +2320,7 @@
|
|||
renesas,fcp = <&fcpf1>;
|
||||
};
|
||||
|
||||
hdmi0: hdmi0@fead0000 {
|
||||
hdmi0: hdmi@fead0000 {
|
||||
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0 0xfead0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -2044,7 +2345,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
hdmi1: hdmi1@feae0000 {
|
||||
hdmi1: hdmi@feae0000 {
|
||||
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
|
||||
reg = <0 0xfeae0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -2118,9 +2419,9 @@
|
|||
|
||||
tsc: thermal@e6198000 {
|
||||
compatible = "renesas,r8a7795-thermal";
|
||||
reg = <0 0xe6198000 0 0x68>,
|
||||
<0 0xe61a0000 0 0x5c>,
|
||||
<0 0xe61a8000 0 0x5c>;
|
||||
reg = <0 0xe6198000 0 0x100>,
|
||||
<0 0xe61a0000 0 0x100>,
|
||||
<0 0xe61a8000 0 0x100>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -2130,49 +2431,114 @@
|
|||
#thermal-sensor-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(8) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
trips {
|
||||
sensor1_crit: sensor1-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
||||
trips {
|
||||
sensor1_passive: sensor1-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
sensor1_crit: sensor1-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor1_passive>;
|
||||
cooling-device = <&a57_0 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
sensor2_crit: sensor2-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
||||
trips {
|
||||
sensor2_passive: sensor2-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
sensor2_crit: sensor2-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor2_passive>;
|
||||
cooling-device = <&a57_0 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
trips {
|
||||
sensor3_crit: sensor3-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
||||
trips {
|
||||
sensor3_passive: sensor3-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
sensor3_crit: sensor3-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor3_passive>;
|
||||
cooling-device = <&a57_0 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* External USB clocks - can be overridden by the board */
|
||||
usb3s0_clk: usb3s0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -27,98 +27,6 @@
|
|||
i2c7 = &i2c_dvfs;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
a53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
a53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
a53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
a53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller-1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The external audio clocks are configured as 0 Hz fixed frequency
|
||||
* clocks by default.
|
||||
|
@ -149,15 +57,203 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57","arm,armv8";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
a53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
a53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
a53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller-1 {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
extal_clk: extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
extalr_clk: extalr {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board */
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
opp-microvolt = <900000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp-1700000000 {
|
||||
opp-hz = /bits/ 64 <1700000000>;
|
||||
opp-microvolt = <900000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <960000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1200000000 {
|
||||
opp-hz = /bits/ 64 <1200000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1300000000 {
|
||||
opp-hz = /bits/ 64 <1300000000>;
|
||||
opp-microvolt = <820000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
/* External PCIe clock - can be overridden by the board */
|
||||
pcie_bus_clk: pcie_bus {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External PCIe clock - can be overridden by the board */
|
||||
pcie_bus_clk: pcie_bus {
|
||||
pmu_a57 {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a57_0>, <&a57_1>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
|
@ -187,18 +283,6 @@
|
|||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
wdt0: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a7796-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
|
@ -211,7 +295,7 @@
|
|||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -226,7 +310,7 @@
|
|||
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -241,7 +325,7 @@
|
|||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -256,7 +340,7 @@
|
|||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -271,7 +355,7 @@
|
|||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -286,7 +370,7 @@
|
|||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -301,7 +385,7 @@
|
|||
|
||||
gpio6: gpio@e6055400 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6055400 0 0x50>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -316,7 +400,7 @@
|
|||
|
||||
gpio7: gpio@e6055800 {
|
||||
compatible = "renesas,gpio-r8a7796",
|
||||
"renesas,gpio-rcar";
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6055800 0 0x50>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
|
@ -334,24 +418,98 @@
|
|||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
pmu_a57 {
|
||||
compatible = "arm,cortex-a57-pmu";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a57_0>,
|
||||
<&a57_1>;
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&a53_0>,
|
||||
<&a53_1>,
|
||||
<&a53_2>,
|
||||
<&a53_3>;
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 8>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 5>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_pv1: mmu@fd950000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xfd950000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
power-domains = <&sysc R8A7796_PD_A3IR>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a7796";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
|
@ -380,6 +538,22 @@
|
|||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -797,7 +971,8 @@
|
|||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii-txid";
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
@ -1082,6 +1257,14 @@
|
|||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
||||
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
||||
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
||||
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
|
||||
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
|
||||
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
|
||||
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
|
||||
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
|
@ -1116,6 +1299,14 @@
|
|||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
|
||||
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
|
||||
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
|
||||
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
|
||||
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
|
@ -1150,6 +1341,14 @@
|
|||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
|
||||
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
|
||||
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
|
||||
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
|
||||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
audma0: dma-controller@ec700000 {
|
||||
|
@ -1184,6 +1383,14 @@
|
|||
resets = <&cpg 502>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
|
||||
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
|
||||
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
|
||||
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
|
||||
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
|
||||
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
|
||||
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
|
||||
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
|
||||
};
|
||||
|
||||
audma1: dma-controller@ec720000 {
|
||||
|
@ -1218,6 +1425,14 @@
|
|||
resets = <&cpg 501>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
|
||||
<&ipmmu_mp 18>, <&ipmmu_mp 19>,
|
||||
<&ipmmu_mp 20>, <&ipmmu_mp 21>,
|
||||
<&ipmmu_mp 22>, <&ipmmu_mp 23>,
|
||||
<&ipmmu_mp 24>, <&ipmmu_mp 25>,
|
||||
<&ipmmu_mp 26>, <&ipmmu_mp 27>,
|
||||
<&ipmmu_mp 28>, <&ipmmu_mp 29>,
|
||||
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
|
@ -1265,6 +1480,19 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3_phy0: usb-phy@e65ee000 {
|
||||
compatible = "renesas,r8a7796-usb3-phy",
|
||||
"renesas,rcar-gen3-usb3-phy";
|
||||
reg = <0 0xe65ee000 0 0x90>;
|
||||
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
|
||||
<&usb_extal_clk>;
|
||||
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 328>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
compatible = "renesas,xhci-r8a7796",
|
||||
"renesas,rcar-gen3-xhci";
|
||||
|
@ -1276,6 +1504,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3_peri0: usb@ee020000 {
|
||||
compatible = "renesas,r8a7796-usb3-peri",
|
||||
"renesas,rcar-gen3-usb3-peri";
|
||||
reg = <0 0xee020000 0 0x400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 328>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 328>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
|
@ -1358,7 +1597,8 @@
|
|||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7796";
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
|
@ -1369,7 +1609,8 @@
|
|||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a7796";
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
|
@ -1380,7 +1621,8 @@
|
|||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7796";
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
|
@ -1391,7 +1633,8 @@
|
|||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7796";
|
||||
compatible = "renesas,sdhi-r8a7796",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
|
@ -1403,9 +1646,9 @@
|
|||
|
||||
tsc: thermal@e6198000 {
|
||||
compatible = "renesas,r8a7796-thermal";
|
||||
reg = <0 0xe6198000 0 0x68>,
|
||||
<0 0xe61a0000 0 0x5c>,
|
||||
<0 0xe61a8000 0 0x5c>;
|
||||
reg = <0 0xe6198000 0 0x100>,
|
||||
<0 0xe61a0000 0 0x100>,
|
||||
<0 0xe61a8000 0 0x100>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -1416,50 +1659,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
||||
trips {
|
||||
sensor1_crit: sensor1-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
||||
trips {
|
||||
sensor2_crit: sensor2-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
||||
trips {
|
||||
sensor3_crit: sensor3-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
|
@ -1657,13 +1856,25 @@
|
|||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pciec1: pcie@ee800000 {
|
||||
reg = <0 0xee800000 0 0x80000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
fdp1@fe940000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe940000 0 0x2400>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 119>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 119>;
|
||||
renesas,fcp = <&fcpf0>;
|
||||
};
|
||||
|
||||
fcpf0: fcp@fe950000 {
|
||||
compatible = "renesas,fcpf";
|
||||
reg = <0 0xfe950000 0 0x200>;
|
||||
|
@ -1708,11 +1919,12 @@
|
|||
clocks = <&cpg CPG_MOD 611>;
|
||||
power-domains = <&sysc R8A7796_PD_A3VC>;
|
||||
resets = <&cpg 611>;
|
||||
iommus = <&ipmmu_vc0 19>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x4000>;
|
||||
reg = <0 0xfea20000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
|
@ -1727,11 +1939,12 @@
|
|||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x4000>;
|
||||
reg = <0 0xfea28000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 622>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
|
@ -1746,11 +1959,12 @@
|
|||
clocks = <&cpg CPG_MOD 602>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 602>;
|
||||
iommus = <&ipmmu_vi0 9>;
|
||||
};
|
||||
|
||||
vspd2: vsp@fea30000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea30000 0 0x4000>;
|
||||
reg = <0 0xfea30000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 621>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
|
@ -1765,6 +1979,7 @@
|
|||
clocks = <&cpg CPG_MOD 601>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 601>;
|
||||
iommus = <&ipmmu_vi0 10>;
|
||||
};
|
||||
|
||||
hdmi0: hdmi@fead0000 {
|
||||
|
@ -1852,4 +2067,105 @@
|
|||
resets = <&cpg 822>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 0>;
|
||||
|
||||
trips {
|
||||
sensor1_passive: sensor1-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
sensor1_crit: sensor1-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor1_passive>;
|
||||
cooling-device = <&a57_0 5 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sensor_thermal2: sensor-thermal2 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 1>;
|
||||
|
||||
trips {
|
||||
sensor2_passive: sensor2-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
sensor2_crit: sensor2-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor2_passive>;
|
||||
cooling-device = <&a57_0 5 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sensor_thermal3: sensor-thermal3 {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&tsc 2>;
|
||||
|
||||
trips {
|
||||
sensor3_passive: sensor3-passive {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
sensor3_crit: sensor3-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor3_passive>;
|
||||
cooling-device = <&a57_0 5 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* External USB clocks - can be overridden by the board */
|
||||
usb3s0_clk: usb3s0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -18,6 +18,10 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
i2c7 = &i2c_dvfs;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
|
@ -47,7 +51,6 @@
|
|||
|
||||
L2_CA57: cache-controller-0 {
|
||||
compatible = "cache";
|
||||
reg = <0>;
|
||||
power-domains = <&sysc 12>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
|
@ -317,7 +320,19 @@
|
|||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
/* placeholder */
|
||||
compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xe61c0000 0 0x200>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
|
@ -523,56 +538,109 @@
|
|||
compatible = "renesas,etheravb-r8a77965",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15",
|
||||
"ch16", "ch17", "ch18", "ch19",
|
||||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii-txid";
|
||||
phy-mode = "rgmii";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi20: csi2@fea80000 {
|
||||
reg = <0 0xfea80000 0 0x10000>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
csi40: csi2@feaa0000 {
|
||||
reg = <0 0xfeaa0000 0 0x10000>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
reg = <0 0xe6ef0000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin1: video@e6ef1000 {
|
||||
reg = <0 0xe6ef1000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin2: video@e6ef2000 {
|
||||
reg = <0 0xe6ef2000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin3: video@e6ef3000 {
|
||||
reg = <0 0xe6ef3000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin4: video@e6ef4000 {
|
||||
reg = <0 0xe6ef4000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin5: video@e6ef5000 {
|
||||
reg = <0 0xe6ef5000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin6: video@e6ef6000 {
|
||||
reg = <0 0xe6ef6000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
vin7: video@e6ef7000 {
|
||||
reg = <0 0xe6ef7000 0 0x1000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
ohci0: usb@ee080000 {
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
|
@ -602,6 +670,7 @@
|
|||
};
|
||||
|
||||
ohci1: usb@ee0a0000 {
|
||||
reg = <0 0xee0a0000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
|
@ -619,69 +688,107 @@
|
|||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
reg = <0 0xe6500000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c1: i2c@e6508000 {
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c2: i2c@e6510000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c3: i2c@e66d0000 {
|
||||
reg = <0 0xe66d0000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c4: i2c@e66d8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg = <0 0xe66d8000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c5: i2c@e66e0000 {
|
||||
reg = <0 0xe66e0000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c6: i2c@e66e8000 {
|
||||
reg = <0 0xe66e8000 0 0x40>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
i2c_dvfs: i2c@e60b0000 {
|
||||
/* placeholder */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,iic-r8a77965",
|
||||
"renesas,rcar-gen3-iic",
|
||||
"renesas,rmobile-iic";
|
||||
reg = <0 0xe60b0000 0 0x425>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 926>;
|
||||
power-domains = <&sysc 32>;
|
||||
resets = <&cpg 926>;
|
||||
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
reg = <0 0xe6e30000 0 8>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm1: pwm@e6e31000 {
|
||||
reg = <0 0xe6e31000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm2: pwm@e6e32000 {
|
||||
reg = <0 0xe6e32000 0 8>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm3: pwm@e6e33000 {
|
||||
reg = <0 0xe6e33000 0 8>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm4: pwm@e6e34000 {
|
||||
reg = <0 0xe6e34000 0 8>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm5: pwm@e6e35000 {
|
||||
reg = <0 0xe6e35000 0 8>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pwm6: pwm@e6e36000 {
|
||||
reg = <0 0xe6e36000 0 8>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
reg = <0 0xfeb00000 0 0x80000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
/* placeholder */
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
|
@ -701,18 +808,26 @@
|
|||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pciec0: pcie@fe000000 {
|
||||
reg = <0 0xfe000000 0 0x80000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
pciec1: pcie@ee800000 {
|
||||
reg = <0 0xee800000 0 0x80000>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
/* placeholder */
|
||||
|
||||
rcar_sound,dvc {
|
||||
|
@ -801,10 +916,13 @@
|
|||
};
|
||||
|
||||
usb3_phy0: usb-phy@e65ee000 {
|
||||
reg = <0 0xe65ee000 0 0x90>;
|
||||
#phy-cells = <0>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
usb3_peri0: usb@ee020000 {
|
||||
reg = <0 0xee020000 0 0x400>;
|
||||
/* placeholder */
|
||||
};
|
||||
|
||||
|
@ -820,6 +938,7 @@
|
|||
};
|
||||
|
||||
wdt0: watchdog@e6020000 {
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
/* placeholder */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -31,6 +31,20 @@
|
|||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <16666666>;
|
||||
};
|
||||
|
@ -39,24 +53,31 @@
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
io_expander: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
scif0_pins: scif0 {
|
||||
groups = "scif0_data";
|
||||
function = "scif0";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_b";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
avb_pins: avb {
|
||||
groups = "avb0_mdc";
|
||||
function = "avb0";
|
||||
};
|
||||
};
|
||||
|
||||
&rpc {
|
||||
|
@ -78,27 +99,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -6,18 +6,22 @@
|
|||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/r8a77970-sysc.h>
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a77970";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
@ -28,15 +32,15 @@
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0>;
|
||||
clocks = <&cpg CPG_CORE 0>;
|
||||
power-domains = <&sysc 5>;
|
||||
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
|
||||
power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_CA53: cache-controller {
|
||||
compatible = "cache";
|
||||
power-domains = <&sysc 21>;
|
||||
power-domains = <&sysc R8A77970_PD_CA53_SCU>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
@ -56,6 +60,11 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
|
@ -84,20 +93,18 @@
|
|||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
rwdt: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a77970-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
clocks = <&cpg CPG_MOD 402>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 402>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
|
@ -121,9 +128,142 @@
|
|||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pfc: pfc@e6060000 {
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 9>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
power-domains = <&sysc R8A77970_PD_A3IR>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 7>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77970";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6060000 {
|
||||
compatible = "renesas,pfc-r8a77970";
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
reg = <0 0xe6060000 0 0x504>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6050000 0 0x50>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 22>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 912>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 912>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6051000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6051000 0 0x50>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 28>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 911>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 911>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6052000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6052000 0 0x50>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 910>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 910>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6053000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6053000 0 0x50>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 17>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 909>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 909>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6054000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6054000 0 0x50>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 6>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 908>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 908>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6055000 {
|
||||
compatible = "renesas,gpio-r8a77970",
|
||||
"renesas,rcar-gen3-gpio";
|
||||
reg = <0 0xe6055000 0 0x50>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 15>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 907>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
|
@ -138,7 +278,7 @@
|
|||
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 407>;
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
|
@ -165,10 +305,14 @@
|
|||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
|
@ -189,10 +333,99 @@
|
|||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe6500000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 931>;
|
||||
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
|
||||
<&dmac2 0x91>, <&dmac2 0x90>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6508000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 930>;
|
||||
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
|
||||
<&dmac2 0x93>, <&dmac2 0x92>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6510000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 929>;
|
||||
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
|
||||
<&dmac2 0x95>, <&dmac2 0x94>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e66d0000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe66d0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 928>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 928>;
|
||||
dmas = <&dmac1 0x97>, <&dmac1 0x96>,
|
||||
<&dmac2 0x97>, <&dmac2 0x96>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@e66d8000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe66d8000 0 0x40>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 927>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 927>;
|
||||
dmas = <&dmac1 0x99>, <&dmac1 0x98>,
|
||||
<&dmac2 0x99>, <&dmac2 0x98>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hscif0: serial@e6540000 {
|
||||
|
@ -202,13 +435,13 @@
|
|||
reg = <0 0xe6540000 0 96>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 520>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
|
||||
<&dmac2 0x31>, <&dmac2 0x30>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 520>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -220,13 +453,13 @@
|
|||
reg = <0 0xe6550000 0 96>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 519>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
|
||||
<&dmac2 0x33>, <&dmac2 0x32>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 519>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -238,13 +471,13 @@
|
|||
reg = <0 0xe6560000 0 96>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 518>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
|
||||
<&dmac2 0x35>, <&dmac2 0x34>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 518>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -255,13 +488,13 @@
|
|||
reg = <0 0xe66a0000 0 96>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 517>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
|
||||
<&dmac2 0x37>, <&dmac2 0x36>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 517>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -273,13 +506,13 @@
|
|||
reg = <0 0xe6e60000 0 64>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 207>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
||||
<&dmac2 0x51>, <&dmac2 0x50>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 207>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -291,13 +524,13 @@
|
|||
reg = <0 0xe6e68000 0 64>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 206>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
||||
<&dmac2 0x53>, <&dmac2 0x52>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 206>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -309,13 +542,13 @@
|
|||
reg = <0 0xe6c50000 0 64>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 204>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
|
||||
<&dmac2 0x57>, <&dmac2 0x56>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 204>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -326,13 +559,13 @@
|
|||
reg = <0 0xe6c40000 0 64>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 203>,
|
||||
<&cpg CPG_CORE 9>,
|
||||
<&cpg CPG_CORE R8A77970_CLK_S2D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
|
||||
<&dmac2 0x59>, <&dmac2 0x58>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 203>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -340,7 +573,7 @@
|
|||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77970",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -374,9 +607,10 @@
|
|||
"ch20", "ch21", "ch22", "ch23",
|
||||
"ch24";
|
||||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc 32>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_rt 3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
@ -389,4 +623,12 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -24,11 +24,61 @@
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x18000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
|
@ -43,6 +93,21 @@
|
|||
};
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
groups = "i2c0";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
groups = "i2c1";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
pwm0_pins: pwm0 {
|
||||
groups = "pwm0_c";
|
||||
function = "pwm0";
|
||||
|
@ -58,12 +123,56 @@
|
|||
function = "scif2";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "mmc_data8", "mmc_ctrl";
|
||||
function = "mmc";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
||||
groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -77,6 +186,7 @@
|
|||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
|
@ -94,6 +204,20 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
/* used for on-board eMMC */
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
@ -48,6 +48,18 @@
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
@ -78,18 +90,6 @@
|
|||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
rwdt: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a77995-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
|
@ -100,11 +100,88 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ipmmu_vi0: mmu@febd0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfebd0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vp0: mmu@fe990000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe990000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_vc0: mmu@fe6b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfe6b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_pv0: mmu@fd800000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xfd800000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_hc: mmu@e6570000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6570000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_rt: mmu@ffc80000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xffc80000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mp: mmu@ec670000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xec670000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe6740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_ds1: mmu@e7740000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe7740000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77995";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77995-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
@ -152,6 +229,78 @@
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe6700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 219>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 218>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
compatible = "renesas,dmac-r8a77995",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 217>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6050000 {
|
||||
compatible = "renesas,gpio-r8a77995",
|
||||
"renesas,rcar-gen3-gpio",
|
||||
|
@ -264,10 +413,67 @@
|
|||
resets = <&cpg 906>;
|
||||
};
|
||||
|
||||
can0: can@e6c30000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c30000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6c38000 {
|
||||
compatible = "renesas,can-r8a77995",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c38000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77995-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
avb: ethernet@e6800000 {
|
||||
compatible = "renesas,etheravb-r8a77995",
|
||||
"renesas,etheravb-rcar-gen3";
|
||||
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
|
||||
reg = <0 0xe6800000 0 0x800>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -303,7 +509,8 @@
|
|||
clocks = <&cpg CPG_MOD 812>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii-txid";
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
@ -318,11 +525,81 @@
|
|||
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,i2c-r8a77995",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe6500000 0 0x40>;
|
||||
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 931>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 931>;
|
||||
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
|
||||
<&dmac2 0x91>, <&dmac2 0x90>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@e6508000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,i2c-r8a77995",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 930>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 930>;
|
||||
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
|
||||
<&dmac2 0x93>, <&dmac2 0x92>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@e6510000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,i2c-r8a77995",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe6510000 0 0x40>;
|
||||
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 929>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 929>;
|
||||
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
|
||||
<&dmac2 0x95>, <&dmac2 0x94>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@e66d0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,i2c-r8a77995",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
reg = <0 0xe66d0000 0 0x40>;
|
||||
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 928>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 928>;
|
||||
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
|
||||
dma-names = "tx", "rx";
|
||||
i2c-scl-internal-delay-ns = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 0x8>;
|
||||
|
@ -363,6 +640,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77995",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 312>;
|
||||
max-frequency = <200000000>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 312>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@ee080100 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
|
@ -400,6 +689,98 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
vspbs: vsp@fe960000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfe960000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 627>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 627>;
|
||||
renesas,fcp = <&fcpvb0>;
|
||||
};
|
||||
|
||||
fcpvb0: fcp@fe96f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfe96f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 607>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 607>;
|
||||
iommus = <&ipmmu_vp0 5>;
|
||||
};
|
||||
|
||||
vspd0: vsp@fea20000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea20000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 623>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 623>;
|
||||
renesas,fcp = <&fcpvd0>;
|
||||
};
|
||||
|
||||
fcpvd0: fcp@fea27000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea27000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 603>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 603>;
|
||||
iommus = <&ipmmu_vi0 8>;
|
||||
};
|
||||
|
||||
vspd1: vsp@fea28000 {
|
||||
compatible = "renesas,vsp2";
|
||||
reg = <0 0xfea28000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 622>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 622>;
|
||||
renesas,fcp = <&fcpvd1>;
|
||||
};
|
||||
|
||||
fcpvd1: fcp@fea2f000 {
|
||||
compatible = "renesas,fcpv";
|
||||
reg = <0 0xfea2f000 0 0x200>;
|
||||
clocks = <&cpg CPG_MOD 602>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 602>;
|
||||
iommus = <&ipmmu_vi0 9>;
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a77995";
|
||||
reg = <0 0xfeb00000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
vsps = <&vspd0 0 &vspd1 0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_lvds0: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
|
@ -408,4 +789,12 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -52,7 +52,7 @@
|
|||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
|
@ -255,9 +255,8 @@
|
|||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
|
@ -265,6 +264,7 @@
|
|||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -283,6 +283,7 @@
|
|||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -295,6 +296,7 @@
|
|||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -337,6 +339,13 @@
|
|||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
pca9654: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
csa_vdd: adc@7c {
|
||||
compatible = "maxim,max9611";
|
||||
reg = <0x7c>;
|
||||
|
@ -354,9 +363,34 @@
|
|||
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@30 {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
compatible = "rohm,bd9571mwv";
|
||||
reg = <0x30>;
|
||||
interrupt-parent = <&intc_ex>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
regulators {
|
||||
dvfs: dvfs {
|
||||
regulator-name = "dvfs";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1030000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -382,8 +416,7 @@
|
|||
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_phy_int", "avb_mdc",
|
||||
"avb_mii";
|
||||
groups = "avb_link", "avb_mdc", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
|
@ -409,6 +442,11 @@
|
|||
function = "i2c2";
|
||||
};
|
||||
|
||||
irq0_pins: irq0 {
|
||||
groups = "intc_ex_irq0";
|
||||
function = "intc_ex";
|
||||
};
|
||||
|
||||
pwm1_pins: pwm1 {
|
||||
groups = "pwm1_a";
|
||||
function = "pwm1";
|
||||
|
@ -497,6 +535,11 @@
|
|||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
usb30_pins: usb30 {
|
||||
groups = "usb30";
|
||||
function = "usb30";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
|
@ -576,10 +619,7 @@
|
|||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
|
||||
max-frequency = <208000000>;
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
|
@ -591,12 +631,10 @@
|
|||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
fixed-emmc-driver-type = <1>;
|
||||
status = "okay";
|
||||
|
||||
max-frequency = <200000000>;
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
|
@ -610,16 +648,17 @@
|
|||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
|
||||
max-frequency = <208000000>;
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&usb_extal_clk {
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
@ -635,11 +674,29 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_peri0 {
|
||||
phys = <&usb3_phy0>;
|
||||
phy-names = "usb";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3s0_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&wdt0 {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xhci0 {
|
||||
pinctrl-0 = <&usb30_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -24,15 +24,6 @@
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpld {
|
||||
compatible = "renesas,ulcb-cpld";
|
||||
status = "okay";
|
||||
gpio-sck = <&gpio6 8 0>;
|
||||
gpio-mosi = <&gpio6 7 0>;
|
||||
gpio-miso = <&gpio6 10 0>;
|
||||
gpio-sstbz = <&gpio2 3 0>;
|
||||
};
|
||||
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
|
@ -40,7 +31,7 @@
|
|||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
clock-frequency = <12288000>;
|
||||
};
|
||||
|
||||
hdmi0-out {
|
||||
|
@ -154,9 +145,8 @@
|
|||
&avb {
|
||||
pinctrl-0 = <&avb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
|
@ -164,9 +154,14 @@
|
|||
reg = <0>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -260,8 +255,7 @@
|
|||
|
||||
avb_pins: avb {
|
||||
mux {
|
||||
groups = "avb_link", "avb_phy_int", "avb_mdc",
|
||||
"avb_mii";
|
||||
groups = "avb_link", "avb_mdc", "avb_mii";
|
||||
function = "avb";
|
||||
};
|
||||
|
||||
|
|
Loading…
Add table
Reference in a new issue