The P3041DS & P5020DS boards are almost identical (except for the
processor in them). Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.
Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock
configuration.
Additionally, the P3041DS/P5020DS support NAND.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rework and add some new APIs to the fsl_corenet_serdes code for use by
erratum and drivers.
* Rename serdes_get_bank() to serdes_get_bank_by_lane()
* Add serdes_get_first_lane returns which SERDES lane is used by device
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix fdt bportal to pass the bman revision number to kernel via device tree.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
To make sure that machine change operation work successfully, change
timing parameters first before changing machine for chip select on IFC.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If FB address is defined specific address then don't grab memory for LCD
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.
This change will let other SoC which also use ftsmc020
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Move the header file "ftsdmc020.h" (SDRAM Controller)
to "include/faraday" folder.
This change will let other SoC which also use ftsdmc020
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Removed boot_flash_* extern variables.
boot_flash_type was totally unused. The other ones were actually constants, so
they have been replaced with #defines in the board config files.
Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Since addr_sp is a byte address, it should be adjusted by 12 here.
Signed-off-by: Eric Cooper <ecc@cmu.edu>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Wolfgang Denk <wd@denx.de>
CONFIG_OMAP34XX must be checked for existence, not value.
Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The reset sequence/configuration for ehci is highly board specific,
so this will be done in the source for the board, instead of
introducing several CONFIG_* which would be needed to make those
few lines in beagle.c usable across different OMAP boards.
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Move the header file and definitions of fttmr010
power control unit from a320 SoC folder to
"include/faraday" folder.
This change will let other SoC which also use fttmr010
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Add i2c_clk_enable in the cpu specific code, since previous platform it,
while new platform don't need. In the pantheon and armada100 platform,
this function is defined as NULL one.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
ftpmu010 related code has been moved to drivers/power/.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
This allows the reading of EEPROMS on the expansion bus without adding
external pull-ups.
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Drop warnings due to recent commit
ARM: mx31: Print the silicon version
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
factor out boot cause function to common code to avoid
the duplicate code in each board support package
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Commit 5d2c154 (IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers)
renamed mx31-imx-regs.h to imx-regs.h.
Change the file label accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Use the same method of the Linux kernel to print the MX31 silicon version on
boot.
Tested on a MX31PDK with a 2.0 silicon, where it shows:
CPU: Freescale i.MX31 rev 2.0 at 531 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
As exception among the i.MX processors, the i.MX31 has headers
without general names (mx31-regs.h, mx31.h instead of imx-regs.h and
clock.h). This requires several nasty #ifdef in the drivers to
include the correct header. The patch cleans up the driver and
renames the header files as for the other i.MX processors.
Signed-off-by: Stefano Babic <sbabic@denx.de>
The patch add CONFIG_HW_WATCHDOG to be used
with the internal watchdog timer of the MX31
processor. Two function are exported for the
board maintainers:
mxc_hw_watchdog_enable
mxc_hw_watchdog_reset
The board maintainer can decide to use mxc_hw_watchdog_reset as
hw_watchdog_reset, or to implement his own function to reset
the watchdog.
The watchdog timer can be configured with CONFIG_SYS_WD_TIMER_SECS
(value in seconds). The MX31 allows values between 0.5
(CONFIG_SYS_WD_TIMER_SECS = 0) and 128 seconds.
Signed-off-by: Stefano Babic <sbabic@denx.de>
If a regions is reserved in the fdt, then it should not be used. Add
the memreserve regions to the lmb so that u-boot doesn't use them to
store the initrd.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
The previous patch makes u-boot use the full accessible size of ram as
the default boot mapped size if CONFIG_SYS_BOOTMAPSZ is not defined,
which means boot_relocate_fdt() can be changed to depend solely on
CONFIG_OF_LIBFDT.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
This patch adds a function getenv_bootm_mapsize() for obtaining the
size of the early mapped region accessible by the kernel during early
boot. It defaults to CONFIG_SYS_BOOTMAPSZ, or if not defined,
defaults to getenv_bootm_size(), which in turn defaults to the size of
RAM.
getenv_bootm_mapsize() can also be overridden with a "bootm_mapsize"
environmental variable.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
For the calls to boot_relocate_fdt(), boot_get_cmdline(), and
boot_get_kbd(), the value of bootmem_base is always obtained by
calling getenv_bootm_low(). Since the value always comes from the
same source, the calling signature for those functions can be
simplified by making them call getenv_bootm_low() directly.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
This converts tsec to use the new PHY Lib. All of the old PHY support
is ripped out. The old MDIO driver is split off, and placed in
fsl_mdio.c. The initialization is modified to initialize the MDIO
driver as well. The powerpc config file is modified to configure PHYLIB
if TSEC_ENET is configured.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
The Blackfin gpio command isn't terribly Blackfin-specific. So generalize
the few pieces into two new optional helpers:
name_to_gpio() - turn a string name into a GPIO #
gpio_status() - display current pin bindings (think /proc/gpio)
Once these pieces are pulled out, we can relocate the cmd_gpio.c into the
common directory.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Partial linking allows weak functions to be overridden in files containing
only one function. Moving the sc520 override of reset_cpu gets rid of an
ugly #ifdef
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Make the copyright notices in the x86 files consistent and update them with
proper attributions for recent updates
Also fix a few comment style/accuracy and whitespace/blank line issues
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
By including <config.h> in the ld script, CONFIG_SYS_MONITOR_LEN (defined
in the boards config file) can be used in lieu of FLASH_SIZE (defined in
the board specific config.mk)
As this is the last remaining entry in the board specific config.mk, this
file can now be removed
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR
and allow that the architecture-specific default value gets
overwritten by defining the value in the board header file.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-msingle-pic-base is a new gcc option for ppc and
it reduces the size of my u-boot with 6-8 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.
-msingle-pic-base will be in gcc 4.6, however
backported patches are available at
http://bugs.gentoo.org/show_bug.cgi?id=347281
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
The -fPIC flag belongs with -mrelocatable, move it there.
Also change -fPIC to -fpic as this produces smaller
binaries.
However, currently -mrelocatable promotes -fpic to -fPIC, a
fix for this is in upcoming gcc 4.6 or you can apply this small
patch to gcc:
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 8da8410..e4b8280 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -227,7 +227,8 @@ do { \
} \
\
else if (TARGET_RELOCATABLE) \
- flag_pic = 2; \
+ if (!flag_pic) \
+ flag_pic = 2; \
} while (0)
#ifndef RS6000_BI_ARCH
--
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Removed clearing of L2 cache as SRAM as it is not necessary without ECC.
This also speeds up the booting process.
Signed-off-by: Fabian Cenedese <cenedese@indel.ch>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.
Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove the SERDES8 erratum work-around code that only applied to P4080
rev1, which is not supported by this version of U-Boot.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM
and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more
appropriate CONFIG_SYS prefix as well as be consistent with 83xx.
Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The bfin_reset_or_hang function unnecessarily duplicates the panic()
logic based on CONFIG_PANIC_HANG.
This patch deletes 20 lines of code and just calls panic() instead.
This also makes the following generic-restart conversion patch simpler.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some parts lack Bank B in L1 data, so have the linker script fall back to
Bank A when that happens. This way we can still leverage L1 data.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When bootstrapping ourselves on the fly at runtime (via "go"), we need to
turn off the caches to avoid taking software exceptions. Since caches
need CPLBs and CPLBs need exception handlers, but we're about to rewrite
the code in memory where those exception handlers live, we need to turn
off caches first.
This new code also encourages a slight code optimization by storing the
MMR bases in dedicated registers so we don't have to fully load up the
pointer regs multiple times.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the part has no external memory configured, then there will be no os
log for us to check, and any attempt to access that memory will trigger
hardware errors.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Common code already takes care of setting up these defines when a port
hasn't specified them, so punt the duplicate values.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The recent global data changes (making the size autogenerated) broke the
board info handling on Blackfin ports as we were lying and lumping the
bd_t size in with the gd_t size. So use the new dedicated bd_t size to
setup its own address in memory.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use
the one coming from the compiler.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We don't want/use this value for Blackfin boards, so punt it and have the
common code error out when people try to use it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Added SDHCDCR register to GUR struct
* Added SDHCDCR_CD_INV define related to SDHCDCR
* Added Pin Muxing define related to TDM on P102x
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P1021 has some QE pins which need to be set in pmuxcr register before
using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and
UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to
be released after MII access because QE12 pin is muxed with LBCTL signal.
Also added relevant QE support defines unique to P1021.
The P1021 QE is shared on P1012, P1016, and P1025.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
i.e, to those parts that have PHY_CLK_VALID bits in their USB
CONTROL registers:
mpc8308 WU_INT, PHY_CLK_SEL, USB_EN, WU_INT_EN, ULPI_INT_EN
mpc831x PHY_CLK_VALID, WU_INT, CLKIN_SEL, PHY_CLK_SEL, UTMI_PHY_EN,
PLL_RESET, REFSEL, OTG_PORT, KEEP_OTG_ON, LSF_EN, USB_EN,
ULPI_INT_EN
mpc834x USB_EN, ULPI_INT1_EN (MPH only), ULPI_INT0_EN
mpc837x USB_EN, ULPI_INT_EN
(mpc832x, mpc8360 don't have a USB_EHCI_FSL compatible controller)
this prevents non-831x parts from never completing cpu_init_f(),
because the (non-existent) PHY_CLK_VALID bit never gets set.
Reported-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Tested-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up, and the DDR2
type for an SO-RDIMM module was added to the DDR2 switch statement.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kim Phillips <kim.phillips@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit (nanoseconds, clock cycles,
and DDR frequencies), we can easily restructure the computation to use
the "do_div()" function to perform 64-bit/32-bit divide operations.
On 64-bit this change is basically a no-op, because do_div is
implemented as a literal 64-bit divide operation and the instruction
scheduling works out almost the same.
On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is
over 1.1kB of code and thousands of heavily dependent cycles to compute,
all of which is linked from libgcc. Another 1.2kB of code comes in for
the function __umoddi3.
It should be noted that nothing else in U-Boot or the Linux kernel seems
to require a full 64-bit divide on my 32-bit PowerPC.
Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Acked-by: York Sun <yorksun@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We utilize the compatible string to find the node to add fsl,liodn
property to. However P3041 & P5020 don't have "fsl,p4080-pcie"
compatible for their PCIe controllers as they aren't backwards compatible.
Allow the macro's to specify the PCIe compatible to use to allow SoC
uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the
PCIe controllers.
Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix up the device tree property associated with the IEEE 1588 timer
source frequency. Currently we only support the IEEE 1588 timer source
being the internal eTSEC system clock (for those SoCs with IEEE 1588
support). The eTSEC clock is ccb_clk/2.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2
of it. Also we only have one Fman so no need for the code to deal with
a second.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some
additional rules to determining the various frequencies that PME & FMan
IP blocks run at.
We need to take into account:
* Reduced number of Core Complex PLL clusters
* HWA_ASYNC_DIV (allows for /2 or /4 options)
On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs
the PME & FMan blocks utilize the second Core Complex PLL. On SoCs
like p4080 with 4 Core Complex PLLs we utilize the third Core Complex
PLL for PME & FMan blocks.
On P2040/P3041/P5020 we have the added feature that we can divide the
PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080
this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be
set to 0 and this gets a backward compatiable /2 behavior.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR
and SDHC erratum.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.
P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.
Added comments in config_mpc85xx.h to denote single core versions of
processors.
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
