Priyanka Jain 32c8cfb23c fsl_esdhc: Deal with watermark level register related changes ... P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-04-10 11:17:55 -05:00
..
arm	ARMV7: S5P: Fixed register offset in mmc.h	2011-03-27 19:20:21 +02:00
avr32	rename _end to __bss_end__	2011-03-27 19:18:37 +02:00
blackfin	Introduce a new linker flag LDFLAGS_FINAL	2011-03-22 23:32:06 +01:00
i386	Coding Style cleanup: remove trailing empty lines	2011-03-27 21:48:08 +02:00
m68k	rename _end to __bss_end__	2011-03-27 19:18:37 +02:00
microblaze	microblaze: Fix msr handling in interrupt_handler	2011-02-15 15:13:24 +01:00
mips	MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectory	2011-04-02 22:07:12 +09:00
nios2	rename _end to __bss_end__	2011-03-27 19:18:37 +02:00
powerpc	fsl_esdhc: Deal with watermark level register related changes	2011-04-10 11:17:55 -05:00
sh	Coding Style cleanup: remove trailing empty lines	2011-03-27 21:48:08 +02:00
sparc	Replace "FLASH" strings with "Flash" or "flash"	2011-01-19 00:02:37 +01:00
.gitignore	update include/asm/ gitignore after move	2010-05-07 00:17:30 +02:00