Introduces various optimisations that approximately triple the
read data rate from NAND when run on da830evm.
Most of these optimisations depend on the endianess of the machine
and most of them are very similar to optimisations already present
in the Linux Kernel.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Davinci: NAND enable ECC even when not in NAND boot mode
On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Davinci: Configurable NAND chip selects
Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Currently, the last block of NAND devices can't be accessed. This patch
fixes this issue by correcting the boundary checking (off-by-one error).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
Depending on offset, flash size and the number of bad blocks,
get_len_incl_bad may return a too small value which may lead to:
1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the
bad block aware read/write code. This may hurt performance, but does
not have any adverse effects.
2) If there are bad blocks, the nand_{read,write}_skip_bad may choose
the bad block unaware read/write code (if len_incl_bad == *length)
which leads to corrupted data.
Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.
checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:
ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch
As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.
The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
I'll fix these errors in another patch.
Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for NAND devices with a page size of
4K in the DaVinci NAND driver. The layout matches the layout that TI uses
for 4K page size NAND devices in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch add nand_read_buf() for S3C2410 NAND SPL.
In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip,
so nand->select_chip should also be initialized.
Signed-off-by: Hui.Tang <zetalabs@gmail.com>
This patch updates a check condition in the NAND driver.
The check condition is similat to what is in linux/next.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for Flex-OneNAND devices.
Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com>
Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
The syndrome based page read/write routines store ECC, and possibly other
"OOB" data, right after each chunk of ECC'd data. With ECC chunk size of
512 bytes and a large page (2KiB) NAND, the layout is:
data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover
Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines
use a traditional layout -- data OOB, disregarding the prepad and postpad
values -- so when they're used with that type of ECC hardware, those calls
mix up the data and OOB. Which means, in particular, that bad block
tables won't be found on startup, with data corruption and related chaos
ensuing.
The current syndrome-based drivers in mainline all seem to use one chunk
per page; presumably they haven't noticed such bugs.
Fix this, by adding read/write page_raw_syndrome() routines as siblings of
the existing non-raw routines; "raw" just means to bypass the ECC
computations, not change data and OOB layout.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When computing oobavail from the list of free areas in the OOB,
don't assume there will always be an unused slot at the end.
This syncs up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch updates the check condition for determining
whether the ECC corrections has failed.
This makes it similar to what is in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This was originally part of Thomas Gleixner's patch for
adding support for 4KiB pages.
This is not part of the U-Boot NAND driver so updating the
driver with this to sync up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch updates the "chip_shift" calculation in the
NAND driver. This is being done to sync up the NAND driver with
the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
Some of the new spi flash files were missing explicit license lines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes
to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patches 1/4, 2/4 and 3/4 of this series
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch includes the onenand driver for s5pc100
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Add #ifdefs where necessary to not perform relocation fixups. This
allows boards/architectures which support relocation to trim a decent
chunk of code.
Note that this patch doesn't add #ifdefs to architecture-specific code
which does not support relocation.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to
support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND
chips. This ECC mode is similar to NAND_ECC_HW, with the exception of
read_page API that first reads the OOB area, reads the data in chunks,
feeds the ECC from OOB area to the ECC hw engine and perform any
correction on the data as per the ECC status reported by the engine.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds a new "page" parameter to all NAND read_page/read_page_raw
APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the
page information to send the READOOB command and read the OOB area before
the data area.
This patch has been accepted by Andrew Morton and can be found at
http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch
WE would like this to become part of the u-boot GIT as well
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove unused read_spareram and add unlock_all as kernel does
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
see http://www.jedec.org/download/search/jep106Z.pdf
Add some second source legacy flash chips 256x8.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix ECC Correction bug where the byte offset location were double
flipped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the s1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byteoffs = (s1 << 0) & 0x80;
.
.
byteoffs |= (s0 >> 4) & 0x08;
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Fix bug introduced by 9c048b5234.
The cfi_flash.c driver cast the flash buffer size to a uchar in
flash_write_cfibuffer(). On some flash parts, (tested on Numonyx
part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to
uchar to enable buffer sizes to be larger.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This chip is used in a number of boards manufactured by Calao-Systems
which should be supported soon. This driver provides the necessary
spi_read and spi_write functions necessary to communicate with the chip.
Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Legacy NAND had been scheduled for removal. Any boards that use this
were already not building in the previous release due to an #error.
The disk on chip code in common/cmd_doc.c relies on legacy NAND,
and it has also been removed. There is newer disk on chip code
in drivers/mtd/nand; someone with access to hardware and sufficient
time and motivation can try to get that working, but for now disk
on chip is not supported.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Now that the 4xx NAND driver ndfc is moved to the common NAND driver
directory we don't need this #ifdef's anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
a.k.a cfi_mtd.c does as cfi_flash.c does. This also prevents
the TQM834x build from doing a:
cfi_mtd.c:36: error: variably modified 'cfi_mtd_info' at file scope
cfi_mtd.c:37: error: variably modified 'cfi_mtd_names' at file scope
using gcc 4.4.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
For JEDEC flash, we should issue word programming command relative to
base address rather than sector base address. Original source makes
SST Flash fails to program sectors which are not on the 0x10000 boundaries.
e.g.
SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector
is 0x1000 bytes.
Thus, if we issue command to "sector base (0x41000) + offset(0x5555)",
it sends to 0x46555 and the chip fails to recognize that address.
This patch is tested with SST39LF040.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds a NAND driver for the Marvell Kirkwood SoC's
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Scott Wood <scottwood@freescale.com>
The bbt descriptors contains the pointer to the bbt pattern which
are statically initialized memory struct. When relocated to RAM,
these pointers will continue point to NOR flash(or L2 SRAM, or
other boot device). If the contents of NOR flash changed or L2
SRAM disabled, it'll hang the system.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The S3C2410 NAND driver source file is included in the makefile instead of
the object file.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Scott Wood <scottwood@freescale.com>
nand_util currently uses size_t which is arch dependent and not always a
unsigned long. Now use loff_t, as does the linux mtd layer.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped. Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Update chipselect handling in davinci_nand.c so that it can
handle 2 GByte chips the same way Linux does: as one device,
even though it has two halves with independent chip selects.
For such chips the "nand info" command reports:
Device 0: 2x nand0, sector size 128 KiB
Switch to use the default chipselect function unless the board
really needs its own. The logic for the Sonata board moves out
of the driver into board-specific code. (Which doesn't affect
current build breakage if its NAND support is enabled...)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty;
it's also unused by any current boards, and doesn't even match the
main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
on newer chips that support it).
DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths
do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
and 5.0/2.6.18) do ... but only for small pages. Large page support
is really broken (and it's unclear just what software it was trying
to match!), and the ECC layout was making three more bytes available
for use by filesystem (or whatever) code.
Since this option itself seems broken, remove it. Add a comment
about the MV/TI compat issue, and the most straightforward way to
address it (should someone really need to solve it).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Minor cleanup for DaVinci NAND code:
- Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't
be defined when there are multiple chipselect lines in use
(as with common 2 GByte chips).
- Cleanup handling of EMIF control registers
* Only need one pointer pointing to them
* Remove incorrect and unused struct supersetting them
- Use the standard waitfunc; we don't need a custom version
- Partial legacy cleanup:
* Don't initialize every board like it's a DM6446 EVM
* #ifdef a bit more code for BROKEN_ECC
Sanity checked with small page NAND on dm355 and dm6446 EVMs;
and large page on dm355 EVM (packaged as two devices, not one).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch fixes a build problem noticed on Apollon by using
mtd_dev_by_eb() instead of "/" as done in the Linux UBI version.
So this brings the U-Boot UBI version more in sync with the Linux
version again.
Signed-off-by: Stefan Roese <sr@denx.de>
new chips supported:-
MX25L1605D, MX25L3205D, MX25L6405D, MX25L12855E
out of which MX25L6405D and MX25L12855E tested on Kirkwood platforms
Modified the Macronix flash support to use 2 bytes of device id instead of 1
This was required to support MX25L12855E
Signed-off-by: Piyush Shah <spiyush@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Looks like when I was encoding the sector sizes, I forgot to divide by 8
(due to the stupid marketing driven process that declares all sizes in
useless megabits and not megabytes).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
NAND module should not modify EMIF registers unrelated to CS2
that is used for NAND, i.e. do not modify EWAIT config register
or registers for other Chip Selects.
Without this patch, EMIF configurations made in board_init()
will be invalidated.
Signed-off-by: Thomas Lange <thomas@corelatus.se>
This patch adds NAND Flash Controller driver for MPC5121 revision 2.
All device features, except hardware ECC and power management, are
supported.
This NFC driver replaces the one orignally posted by John Rigby:
"[PATCH] Freescale NFC NAND driver"
It's a port of the Linux driver version posted by Piotr Ziecik a few
weeks ago. Using this driver has the following advantages (from my
point of view):
- Compatibility with the Linux NAND driver (e.g. ECC usage)
- Better code quality in general
- Resulting U-Boot image is a bit smaller (approx. 3k)
- Better to sync with newer Linux driver versions
The only disadvantage I can see, is that HW-ECC is not supported right
now. But this could be added later (e.g. port from Linux driver after
it's supported there). Using HW-ECC on the MCP5121 NFC has a general
problem because of the ECC usage in the spare area. This collides with
JFFS2 for example.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Piotr Ziecik <kosmo@semihalf.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
UBI is quite memory greedy and requires at least approx. 512k of malloc
area. This patch adds a compile-time check, so that boards will not
build with less memory reserved for this area (CONFIG_SYS_MALLOC_LEN).
Signed-off-by: Stefan Roese <sr@denx.de>
Added macronix SF driver for MTD framework
MX25L12805D is supported and tested
TBD: sector erase implementation, other deivces support
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This new define enables mtdcore.c compilation and with this we can
select the MTD device infrastructure needed for the reworked mtdparts
command.
We now have the 2 MTD infrastructure defines, CONFIG_MTD_DEVICE and
CONFIG_MTD_PARTITIONS. CONFIG_MTD_DEVICE is needed (as explained above)
for the "mtdparts" command and CONFIG_MTD_PARTITIONS is needed for UBI.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
This patch brings the U-Boot MTD infrastructure in sync with the current
Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size
support and a resync of the mtdpart.c file which has seen multiple fixes
meanwhile.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kyungmin Park <kmpark@infradead.org>
This patch adds concatenation support to the U-Boot MTD infrastructure.
By enabling CONFIG_MTD_CONCAT this MTD CFI wrapper will concatenate
all found NOR devices into one single MTD device. This can be used by
e.g by UBI to access a partition that spans over multiple NOR chips.
Signed-off-by: Stefan Roese <sr@denx.de>
Several boards used different ways to specify the size of the
protected area when enabling flash write protection for the sectors
holding the environment variables: some used CONFIG_ENV_SIZE and
CONFIG_ENV_SIZE_REDUND, some used CONFIG_ENV_SECT_SIZE, and some even
a mix of both for the "normal" and the "redundant" areas.
Normally, this makes no difference at all. However, things are
different when you have to deal with boards that can come with
different types of flash chips, which may have different sector
sizes.
Here we may have to chose CONFIG_ENV_SECT_SIZE such that it fits the
biggest sector size, which may include several sectors on boards using
the smaller sector flash types. In such a case, using CONFIG_ENV_SIZE
or CONFIG_ENV_SIZE_REDUND to enable the protection may lead to the
case that only the first of these sectors get protected, while the
following ones aren't.
This is no real problem, but it can be confusing for the user -
especially on boards that use CONFIG_ENV_SECT_SIZE to protect the
"normal" areas, while using CONFIG_ENV_SIZE_REDUND for the
"redundant" area.
To avoid such inconsistencies, I changed all sucn boards that I found
to consistently use CONFIG_ENV_SECT_SIZE for protection. This should
not cause any functional changes to the code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Paul Ruhland
Cc: Pantelis Antoniou <panto@intracom.gr>
Cc: Stefan Roese <sr@denx.de>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: Dave Ellis <DGE@sixnetio.com>
Acked-by: Stefan Roese <sr@denx.de>
This patch now enabled this cfi-mtd wrapper to correctly detect and
erase the last sector in an NOR FLASH device.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables Smart Media (SMC) ECC byte ordering which is used
on the PPC4xx NAND FLASH controller (NDFC). Without this patch we have
incompatible ECC byte ordering to the Linux kernel NDFC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
With this patch non-uniform NOR FLASH chips (chips with multiple erase
regions) can be exported via the cfi-mtd layer and therefor used by UBI.
We select the largest sector size as erasesize. The cfi driver will make
sure that the smaller sectors are handled correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
With this patch the NAND and OneNAND devices are registered in the MTD
subsystem and can then be referenced by the mtdcore code (e.g.
get_mtd_device_nm()). This is needed for the new "ubi part" command
syntax without the flash type parameter (nor|nand|onenand).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes this compilation warning when CONFIG_MTD_PARTITIONS is
defined:
nand_base.c: In function 'nand_release':
nand_base.c:2922: warning: implicit declaration of function 'del_mtd_partitions'
Signed-off-by: Stefan Roese <sr@denx.de>
Fix dependency goofage: it should certainly be possible to have the
partition support without bringing in UBI commands.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Stefan Roese <sr@denx.de>
We need to make sure the data written to the nand flash controller makes
it there before we start polling its status register. Otherwise, we may
get stale data and return before the controller is actually ready.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Scott Wood <scottwood@freescale.com>
On platforms with multiple NOR chips, currently only the first one
can be selected using the "ubi part" command. This patch fixes this
problem by using different names for the NOR "mtd devices".
It also changes the name of the NOR MTD device from "cfi-mtd" to
"norX" (X indexing the device numer) to better match the mtdparts
defaults.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
The AT91RM9200-EK Evaluation Board supports the AT91RM9200
ARM9-based 32-bit RISC microcontroller and enables real-time code development
and evaluation.
Here is the chip page on Atmel website:
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507
with
- NOR (cfi driver)
- DataFlash
- USB OHCI
- Net
- I2C (hard)
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Legacy NAND is marked for feature removal after April 2009 (i.e. this
upcoming release). There are still several boards that reference it
(though many do so only for disk-on-chip support which has been silently
disabled for a while now). These boards will now fail to build
with #error, though the code is still there if the user removes #error.
The plan is to remove the code outright in the next release, along with
any board code that refers to it (such as board/esd/common/auto_update.c).
Also, remove the legacy NAND API description from README.nand.
Signed-off-by: Scott Wood <scottwood@freescale.com>
I can't find anywhere in the datasheet that says the status register needs
3 dummy bytes sent to it before being able to read back the first real
result. Tests on a Blackfin board show that after writing the opcode, the
status register starts coming back immediately. So only write out the
read status register opcode before polling the result.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Jason McMullan <mcmullan@netapp.com>
CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Since timeouts are only hit when there is a problem in the system, we
don't want to prematurely timeout on a functioning setup. Thus having
low timeouts (in milliseconds) doesn't gain us anything in the production
case, but rather increases likely hood of causing problems where none
otherwise exist.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Some SPI flash drivers like to have extended id information available
(like the spansion flash), so rather than making it re-issue the ID cmd
to get at the last 2 bytes, have the common code read 5 bytes rather than
just 3. This also matches the Linux behavior where it always reads 5 id
bytes from all flashes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Mingkai Hu <Mingkai.hu@freescale.com>
The common SPI flash code reads the idcode and passes it down to the SPI
flash driver, so there is no need to read it again ourselves.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
CC: Jason McMullan <mcmullan@netapp.com>
CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Add MTD SPI Flash support for S25FL008A, S25FL016A,
S25FL032A, S25FL064A, S25FL128P.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The NAND flash on the TQM8548_BE modules requires a short delay after
running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE
requires a further short delay after writing out a buffer. Normally the
R/B pin should be checked, but it's not connected on the TQM8548_BE.
The corresponding Linux FSL UPM driver uses similar delay points at the
same locations. To manage these extra delays in a more general way, I
introduced the "wait_flags" field allowing the board-specific driver to
specify various types of extra delay.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For the NAND chips on the TQM8548 modules, a special chip-select logic is
used. It uses dedicated address lines to be set via UPM machine address
register (mar). This patch adds such support to the FSL-UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for multi-chip NAND devices to the FSL-UPM
driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now
called with the argument "chip_nr" to allow testing the proper chip
select line. The NAND support of the MPC8360ERDK is updated as well.
No other boards are currently using the FSL UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for NAND_MAX_CHIPS to the MTD NAND layer.
Multi-chips devices are displayed as shown:
Device 0: 2x NAND 512MiB 3,3V 8-bit, sector size 128 KiB
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
On the pcm030 the environment is located in the onboard EEPROM. But we want
to handle flash sector protection in a safe manner. So we must read the
unlock environment variable from EEPROM instead from flash.
This patch is required as long the evironment is saved into the EEPROM.
Stefan: Additional change as suggested by Wolfgang, use bigger char array
(instead of 4).
Signed-off-by: Eric Schumann <E.Schumann@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Follow up to the flash_fixup_stm to fix geometry reversal
on STMicro M29W320ET flash chip. The M29W320DT has 4 erase region.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This driver implements the ECC algorithm described in
the CPU data sheet and uses the OOB layout chosen in
already-released development systems (shipped with a custom-made
u-boot 1.3.1).
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
If on your board is more than one flash, you must know
the size of every single flash, for example, for updating
the DTS before booting Linux. So make this function
flash_get_info() extern, and you can have all info
about your flashes.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Without the timeout present an infinite loop can occur if the
NAND device is broken or not present.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Commit cfa460adfd removed support
for disabling the "No NAND device found!!!" warning when
CONFIG_SYS_NAND_QUIET_TEST was defined. This re-adds support
for silencing the warning.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Dear Wolfgang,
You are right, the patch was ugly.
The new one seems to be better.
Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Patch "flash/cfi_flash: Use virtual sector start address, not phys"
introduced a small typo and compilation warning for systems with CFI
legacy support (e.g. hcu4). This patch fixes it.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes the double defined manufacturer defines from
jedec_flash.c. Since the common defines in flash.h are 32bit
we now need the (16) cast. This patch also removes the compilation
warning (e.g. seen on hcu5):
./MAKEALL hcu5
Configuring for hcu5 board...
jedec_flash.c:219: warning: large integer implicitly truncated to unsigned type
Signed-off-by: Stefan Roese <sr@denx.de>
Patch "flash/cfi_flash: Use virtual sector start address, not phys"
introduced a small compilation warning. This patch fixes it.
Signed-off-by: Stefan Roese <sr@denx.de>
include/flash.h was commented to say that the address in
flash_info->start was a physical address. However, from u-boot's
point of view, and looking at most flash code, it makes more
sense for this to be a virtual address. So I corrected the
comment to indicate that this was a virtual address.
The only flash driver that was actually treating the address
as physical was the mtd/cfi_flash driver. However, this code
was using it inconsistently as it actually directly dereferenced
the "start" element, while it used map_physmem to get a
virtual address in other places. I changed this driver so
that the code which initializes the info->start field calls
map_physmem to get a virtual address, eliminating the need for
further map_physmem calls. The code is now consistent.
The *only* place a physical address should be used is when defining the
flash banks list that is used to initialize the flash_info struct,
usually found in the board config file.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Added flash_fixup_stm to fix geometry reversal on STMicro M29W320ET flash chip.
Modeled after flash_fixup_amd, this patch handles the geometry reversal
or erase sectors that exist for ST Micro (now Numonyx) M29W320ET flash.
Since I cannot test all STM's chips, the detection is implemented as
narrow as possible for now.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The function find_sector() doesn't need to be called twice in
the case of AMD command set.
Tested on TQM5200S-BD with Samsung K8P2815UQB.
Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Higher spi flash layers expect to be given back a pointer that was
malloced so that it can free the result, but the lower layers return
a pointer that is in the middle of the malloced memory. Reorder the
members of the lower spi structures so that things work out.
Signed-off-by: Brad Bozarth <bflinux@yumbrad.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and
changes the default from 8 to 1 for the legacy and the new MTD
NAND layer. This allows to remove all NAND_MAX_CHIPS definitions
in the board config files because none of the boards use multi
chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440
define
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
but that's bogus and did not work anyhow.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Enable nand lock, unlock and status of lock feature.
Not every device and platform requires this, hence,
it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK
Nand unlock and status operate on block boundary instead
of page boundary. Details in:
http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT
Intial solution provided by Vikram Pandita <vikram.pandita@ti.com>
Includes preliminary suggestions from Scott Wood
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Rather than putting the function prototype for board_nand_init() in the one
place where it gets called, put it into nand.h so that every place that also
defines it gets the prototype. Otherwise, errors can go silently unnoticed
such as using the wrong return value (void rather than int) when defining
the function.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
- Add subpage write support
- Add onenand_oob_64/32 ecclayout
This has been missing and without it UBI has some incompatibilies issues
with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is
placed differently (2048 instead of 512) without this fix.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The version (ver_id) was not stored in the onenand_chip structure and
because of this the continuous locking scheme could be enabled on some
chips.
Signed-off-by: Stefan Roese <sr@denx.de>
The current code that determines which bank/chipselect is used for a
given NAND instance only worked for 32-bit addresses and assumed
a 1:1 mapping. This breaks in 36-bit physical configs.
The proper way to handle this is to use the virt_to_phys() and
BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address
with the the virtual address the NAND code uses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Scott Wood <scottwood@freescale.com>
Otherwise, recursion can occur if scan_bbt does not find a bad block
table, and tries to write one, and the attempt to erase the BBT area
causes a bad block check.
Signed-off-by: Scott Wood <scottwood@freescale.com>
The stmicro_wait_ready() func tries to show the actual opcode that was sent
to the device, but instead it displays the array pointer. Fix it to pull
out the opcode from the start of the array.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
With this patch now, the user can call "ubi part" multiple times to
re-connect the UBI device to another MTD partition.
Signed-off-by: Stefan Roese <sr@denx.de>
Don't use LIST_HEAD() but initialize the struct via INIT_LIST_HEAD() upon
first call of add_mtd_partitions(). Otherwise this won't work on platforms
where the relocation is broken (like MIPS or PPC).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fix the problem that only the [NB_DATAFLASH_AREA - 1] dataflash
partition can be defined to use the area to the end of dataflash size.
Now it is possible to have only one dataflash partition from 0 to the end
of of dataflash size.
Signed-off-by: Ilko Iliev <iliev@ronetix.at>
This caused the operation to be needlessly repeated if there were
no bad blocks and no errors.
Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Remove a printf() from add_mtd_device(), which produces spurious output.
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add cfi-mtd driver, which exports CFI flash to MTD layer.
This allows CFI flash devices to be used from MTD layer.
Building of the new driver is controlled by CONFIG_FLASH_CFI_MTD
option. Initialization is done by calling cfi_mtd_init() from
flash_init().
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add interface for flash verbosity control. It allows
to disable output from low-level flash API. It is useful
when calling these low-level functions from context other
than flash commands (for example the MTD/CFI interface
implmentation).
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Export flash_sector_size() function from drivers/mtd/cfi_flash.c,
so that it can be used in the upcoming cfi-mtd driver.
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch defines all flash access functions as weak so that
they can be overridden by board specific versions.
This will be used by the upcoming VCTH board support where the NOR
FLASH unfortunately can't be accessed memory-mapped. Special
accessor functions are needed here.
To enable this weak functions you need to define
CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS in your board config header.
Otherwise the "old" default functions will be used resulting
in smaller code.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
It's based on the Linux UBI version and basically has a "OS"
translation wrapper that defines most Linux specific calls
(spin_lock() etc.) into no-ops. Some source code parts have been
uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
this version with the Linux version and simplifies future UBI
ports/bug-fixes from the Linux version.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
It's based on the Linux UBI version and basically has a "OS"
translation wrapper that defines most Linux specific calls
(spin_lock() etc.) into no-ops. Some source code parts have been
uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
this version with the Linux version and simplifies future UBI
ports/bug-fixes from the Linux version.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
It's based on the Linux UBI version and basically has a "OS"
translation wrapper that defines most Linux specific calls
(spin_lock() etc.) into no-ops. Some source code parts have been
uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
this version with the Linux version and simplifies future UBI
ports/bug-fixes from the Linux version.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
It's based on the Linux UBI version and basically has a "OS"
translation wrapper that defines most Linux specific calls
(spin_lock() etc.) into no-ops. Some source code parts have been
uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
this version with the Linux version and simplifies future UBI
ports/bug-fixes from the Linux version.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds basic UBI (Unsorted Block Image) support to U-Boot.
It's based on the Linux UBI version and basically has a "OS"
translation wrapper that defines most Linux specific calls
(spin_lock() etc.) into no-ops. Some source code parts have been
uncommented by "#ifdef UBI_LINUX". This makes it easier to compare
this version with the Linux version and simplifies future UBI
ports/bug-fixes from the Linux version.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This MTD part infrastructure will be used by the upcoming
UBI support.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch fixes a problem on systems where the NOR flash is attached
to a 64 bit bus. The toggle bit detection in flash_toggle() is based
on the assumption that the same flash address is read twice without
any other interjacent flash accesses. However, on 32 bit systems the
function flash_read64() [as currently implemented] does not perform
an atomic 64 bit read - instead, this is broken down into two 32 bit
read accesses on addresses "addr" and "addr + 4". So instead of
reading a 64 bit value twice from "addr", we see a sequence of 4 32
bit reads from "addr", "addr + 4", "addr", and "addr + 4". The
consequence is that flash_toggle() fails to work.
This patch implements a simple, but somewhat ugly solution, as it
avoids the use of flash_read64() in this critical place (by breaking
it down manually into 32 bit read operations) instead of rewriting
flash_read64() such to perform atomic 64 bit reads as one could
expect. However, such a rewrite would require the use of floating
point load operations, which becomes pretty complex:
save MSR;
set Floating Point Enable bit in MSR;
use "lfd" instruction to perform atomic 64 bit read;
use "stfd" to store value to temporary variable on stack;
load u64 value from temporary variable;
restore saved MSR;
return u64 value;
The benefit-cost ratio of such an implementation was considered too
bad to actually attempt this, especially as we can expect that such
an implementation would not only have a bigger memory footprint but
also cause a performance degradation.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
As reported by Ilko Iliev <iliev@ronetix.at>, the "nand erase clean"
command is currently broken, and among other things causes all blocks
to be marked bad.
This implements it properly using MTD_OOB_AUTO, along with some
indentation fixes.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Hardware expects ECCM 0 for small page and ECCM 1 for large page
when booting from NAND, so use those defaults.
Signed-off-by: Scott Wood <scottwood@freescale.com>
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Some chips require a RESET after power-up (e.g. Micron MT29FxGxxxxx).
The first command sent is NAND_CMD_READID.
Issue a NAND_CMD_RESET in nand_scan_ident before reading the device id.
Tested with an MT29F4G08AAC.
Signed-off-by: Karl Beldan <karl.beldan@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This brings the core NAND code up to date with the Linux kernel.
Since there were several drivers in Linux as of the last update that are
not in u-boot, I'm not bringing over new drivers that have been added
since in the absence of an interested party.
I did not update OneNAND since it was recently synced by Kyungmin Park,
and I'm not sure exactly what the common ancestor is.
Signed-off-by: Scott Wood <scottwood@freescale.com>
When the total size of all NAND devices exceeds 4 GiB, the size will
overflow. This patch tries to fix this.
Note that we still have a problem when a single NAND device is bigger
than 4 GiB: then the overflow would actually happen earlier, i. e.
when storing the size in nand_info[].size, as nand_info[].size is an
"u_int32_t".
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
The flash_unlock_seq requires a sector for AMD_LEGACY.
Fix a retcode check typeo.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The CFI flash driver starts at flash_init() which calls down into
flash_get_size(). This starts by calling flash_detect_cfi(). If said
function fails, flash_get_size() finishes by attempting to reset the
flash. Unfortunately, it does this with an info->portwidth set to 0x10
which filters down into flash_make_cmd() and that happily smashes the
stack by sticking info->portwidth bytes into a cfiword_t variable that
lives on the stack. On a 64bit system you probably won't notice, but
killing the last 8 bytes on a 32bit system usually leads to a corrupt
return address. Which is what happens on a Blackfin system.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch deletes oobavail assignments, they're calculated by the nand
core code in nand_scan_tail, plus current oobavail values are wrong for
the LP NANDs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch implements support for flash-based BBT for chips working
through ELBC NAND controller, so that NAND core will not have to re-scan
for bad blocks on every boot.
Because ELBC controller may provide HW-generated ECCs we should adjust
bbt pattern and bbt version positions in the OOB free area.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
For large page chips, nand_bbt is looking into OOB area, and checking
for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be
reserved for bbt means.
But ELBC driver is specifying ecclayout so that oobfree area starts at
offset 1, so only one byte left for the bbt purposes.
This causes problems with any OOB users, namely JFFS2: after first mount
JFFS2 will fill all OOBs with "erased marker", so OOBs will contain:
OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
And on the next boot, NAND core will rescan for bad blocks, then will
see "0xff 0x19" pattern, and will mark all blocks as bad ones.
To fix the issue we should implement our own bad block pattern: just one
byte at OOB start. Though, this will work only for x8 chips. For x16
chips two bytes must be checked. Since ELBC driver does not support x16
NANDs (yet), we're safe for now.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fix printf format-string/arg mismatches under -DDEBUG.
These warnings occur with DEBUG defined for a platform using
cpu/mpc85xx. Users of other architectures can unearth similar
problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right
after "CFLAGS += $(call cc-option,-fno-stack-protector)".
Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch fixes a missing vendor code in the flash_real_protect() function.
Signed-off-by: Nick Spence <nick.spence@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
New implement sector lock and unlock or softlock commands
do not exist in AMD legacy flash. Thus, causing issue
when erasing AMD legacy flash (such as lv040)
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since page size field is changed from oobblock to writesize. But OneNAND is not updated.
- fix bufferram management at erase operation
This patch includes the NAND/OneNAND state filed too.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
