Commit graph

14717 commits

Author SHA1 Message Date
Tom Rini
b4ee6daad7 Porting to DM and i.MX8
------------------------
 
 - warp7 to DM
 - kp_imx53 to DM
 - Warnings in DT
 - MX8QM support
 - colibri-imx6ull to DM
 - imx7d-pico to DM
 - ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Porting to DM and i.MX8
------------------------

- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
2019-05-01 07:25:51 -04:00
Igor Opaniuk
fc1fe01b08 avb: add support for named persistent values
AVB 2.0 spec. revision 1.1 introduces support for named persistent values
that must be tamper evident and allows AVB to store arbitrary key-value
pairs [1].

Introduce implementation of two additional AVB operations
read_persistent_value()/write_persistent_value() for retrieving/storing
named persistent values.

Correspondent pull request in the OP-TEE OS project repo [2].

[1]: https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22
[2]: https://github.com/OP-TEE/optee_os/pull/2699

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2019-04-26 18:58:22 -04:00
Patrick Delaunay
50fd31fd77 sysreset: syscon: remove POWER reset cause
The sysreset of 'POWER' type is a PMIC reset defined as
'remove and restore power'.
So normally only COLD/WARN is supported by sysreset_syscon.

This modification allows to use the function sysreset_walk(SYSRESET_POWER)
when it is supported by PMIC driver (see example in stpmic1).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-04-26 18:58:22 -04:00
Gregory CLEMENT
32dfc12b70 net: lpc32xx: Use IRAM for transmit buffer
Since the introduction of the driver, some memory in IRAM is reserved for
the TX buffers.

However there are not used but instead of it, it is the buffer provided
by the net stack which is used. As stated in the comment of the driver,
not using the IRAM buffer could cause cache issue and lower the
throughput.

For the second argument it is less the case for transmitting buffers
because the throughput gain in IRAM is mitigated by the time to copy the
data from RAM to IRAM, but the first argument is still valid and indeed
this patch fixes issue seen with Ethernet on some boards

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-26 18:58:20 -04:00
Gregory CLEMENT
5f626e7849 mtd: nand: raw: Fix CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT behavior
The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
was to allow disabling the default ECC layouts if a driver is known to
provide its own ECC layout. However, this commit did the opposite and
disabled the default layout when it was _not_ selected.

It breaks all the NAND drivers not providing their own ECC layout this
patch fix this situation.

It was tested with the lpc32xx_nand_slc driver.

Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-26 18:58:20 -04:00
Andrew F. Davis
ff6043a5fd firmware: ti_sci: Modify auth_boot TI-SCI API to match new version
SYSFW version 2019.01 introduces a slightly modified version of this API,
add support for it here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-26 17:51:51 -04:00
Andrew F. Davis
32ca8ffd5b firmware: ti_sci: Add support for firewall management
TI-SCI message protocol provides support for controlling the firewall
configurations available in SoC.

Introduce support for the set of TI-SCI message protocol APIs that
provide us with this capability of controlling firewalls.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
2019-04-26 17:51:51 -04:00
Tom Rini
07b68b7843 Merge git://git.denx.de/u-boot-marvell
- Add DM based generic watchdog start and reset implementation
  and remove all ad-hoc implementations (Stefan)
- Move mv_sdhci to DM (Pierre)
- Misc turris_omnia updates (Pierre)
- Change openrd targets to correctly build again (size changes
  and fixes to the dts targets) and bring it back into Travis
  builds (Stefan)
- Add Kirkwood db-88f6281-bp board (Chris)
2019-04-26 13:50:00 -04:00
Tom Rini
1c64692df2 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2019-04-26 13:49:58 -04:00
Stefan Roese
c2ff69a444 watchdog: at91sam9_wdt: Remove now superfluous wdt start and reset
With the new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).

The watchdog servicing is enabled via CONFIG_WATCHDOG.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
2019-04-26 09:16:32 +02:00
Stefan Roese
f3729ba6e7 watchdog: mpc8xx_wdt: Watchdog driver and macros cleanup
With the generic watchdog driver now implemented, this patch removes
some legacy stuff from the MPC8xx watchdog driver and its Kconfig
integration. CONFIG_MPC8xx_WATCHDOG is completely removed and
hw_watchdog_reset() is made static, as the watchdog will now get
serviced via the DM infrastructure if enabled via CONFIG_WATCHDOG.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
2019-04-26 09:16:32 +02:00
Stefan Roese
782ef57edc watchdog: cadence: Remove driver specific "timeout-sec" handling
Now that we have a generic DT property "timeout-sec" handling, the
driver specific implementation can be dropped.

This patch also changes the timeout restriction to the min and max
values (clipping). Before this patch, the value provided via
"timeout-sec" was used if the parameter was too high or low. Now
the driver specific min and max values are used instead.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
2019-04-26 09:16:32 +02:00
Stefan Roese
06985289d4 watchdog: Implement generic watchdog_reset() version
This patch tries to implement a generic watchdog_reset() function that
can be used by all boards that want to service the watchdog device in
U-Boot. This watchdog servicing is enabled via CONFIG_WATCHDOG.

Without this approach, new boards or platforms needed to implement a
board specific version of this functionality, mostly copy'ing the same
code over and over again into their board or platforms code base.

With this new generic function, the scattered other functions are now
removed to be replaced by the generic one. The new version also enables
the configuration of the watchdog timeout via the DT "timeout-sec"
property (if enabled via CONFIG_OF_CONTROL).

This patch also adds a new flag to the GD flags, to flag that the
watchdog is ready to use and adds the pointer to the watchdog device
to the GD. This enables us to remove the global "watchdog_dev"
variable, which was prone to cause problems because of its potentially
very early use in watchdog_reset(), even before the BSS is cleared.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Maxim Sloyko <maxims@google.com>
Cc: Erik van Luijk <evanluijk@interact.nl>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: "Álvaro Fernández Rojas" <noltari@gmail.com>
Cc: Philippe Reynes <philippe.reynes@softathome.com>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
2019-04-26 09:16:32 +02:00
Pierre Bourdon
4ec9dd4071 mmc: mv_sdhci: add driver model support
The new DM implementation currently does not support the Sheeva
88SV331xV5 specific quirk present in the legacy implementation. The
legacy code is thus kept for this SoC and others not yet migrated to
DM_MMC.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-04-26 07:35:38 +02:00
Peng Fan
5e479ccdf1 ddr: imx8m: hide i.MX8M DDR options from device driver entry
Use one menu to hide the several i.MX8M DDR options from device
driver entry.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:20:04 +02:00
Ye Li
b3cf86c86b mxc_ocotp: Disable fuse sense for imx8mq B1
On iMX8MQ Rev B1, reading from fuse box is not allowed. The
OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa
for chip rev. So u-boot has to disable the fuse sense function for it.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:16:24 +02:00
Ye Li
112ad60058 mxc_ocotp: Update redundancy banks for mx7ulp B0
On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to
Redundancy mode not ECC, so they can support to program different bits of
a word in multiple times.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 19:16:24 +02:00
Peng Fan
894e02b7b0 misc: imx8: scu: add i.MX8QM support
According to IMX8QXP/8QM config option, choose the clk/iomuxc
compatible.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
e45efe90cd clk: imx8: add i.MX8QM clk driver
Add i.MX8QM clk driver, SDHC/FEC/UART/I2C supported.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
98c63a7840 clk: imx8: split code into common and soc specific part
To make it easy to add new clk driver for i.MX8, split
the code into common part and SoC specific part.

Make the get/set/enable non static and introduce a num_clks for
soc_clk_dump, because the arrays are moved to clk-imx8qxp.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Peng Fan
a413c17e41 pinctrl: imx8: add i.MX8QM compatible
Add i.MX8QM compatible

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
400b972a7e Convert CONFIG_USB_EHCI_MX5 to Kconfig
This converts the following to Kconfig:
   CONFIG_USB_EHCI_MX5

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Lukasz Majewski
22988766da USB: DM: Convert i.MX5 ehci code to driver model
This commit converts i.MX5's EHCI USB host driver to driver model (DM_USB).
It is a straightforward conversion (to reuse as much code as possible),
based on ehci-mx6.c code.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-04-25 17:03:25 +02:00
Peng Fan
90c98a5ad0 imx8: fuse: add fuse driver
Add fuse write for i.MX8

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-04-25 09:03:15 +02:00
Simon Goldschmidt
4e829e9841 rtc: m41t62: add compatible for m41t82
This adds a compatible string for m41t82. This ensures that this driver
can be used for m41t82 in DM mode, too (asit was usable for this model in
non-DM mode before).

In addition, the HT bit has to be reset during probe, since the m41t82
chip sets it when entering battery standby mode.

This patch ensures this driver works on socfpga_socrates.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-04-25 00:00:49 +02:00
Simon Goldschmidt
36821b3f55 i2c: designware: fix reset handling on socfpga gen5
Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort
as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide
reset-names).

The actual bug was to check 'if (&priv->reset_ctl)', which is never false.

While at it, convert the driver to use 'reset_get_bulk' instead of looking
at a specific named reset and also make it release the reset on driver
remove before starting the OS.

Fixes: 622597dee4 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-04-25 00:00:49 +02:00
Tom Rini
7d99406742 Various minor sandbox iumprovements
Fixes for tracing with sandbox
 Refactoring for boot_get_fdt()
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Merge tag 'pull-24apr19' of git://git.denx.de/u-boot-dm

Various minor sandbox iumprovements
Fixes for tracing with sandbox
Refactoring for boot_get_fdt()
2019-04-24 12:27:29 -04:00
Tom Rini
c2bb9c5b9e STM32 MCUs update:
_ DT rework and alignment with DT kernel v4.20
 _ mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
 _ mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
 _ configs: update for F746/769 boards
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Merge tag 'u-boot-stm32-mcu-20190423' of https://github.com/pchotard/u-boot

STM32 MCUs update:
- DT rework and alignment with DT kernel v4.20
- mmc: arm_pl180_mmci: Synchronize compatible with kernel v4.20
- mmc: stm32_sdmmc2: Synchronize properties with kernel v4.20
- configs: update for F746/769 boards
2019-04-24 12:26:39 -04:00
Tom Rini
ceb6ddbc73 - Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
 - Add support for the Libretech-AC AML-S805X-AC board
 - Add Amlogic AXG reset compatible
 - Add I2C support for Amlogic AXG
 - Fix AXG PIN and BANK pinctrl definitions
 - Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
 - Add initial support for Amlogic G12A SoC and U200 board
 - Enable PHY_REALTEK for selected boards
 - Fix Khadas VIM2 README
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Merge tag 'u-boot-amlogic-20190423' of git://git.denx.de/u-boot-amlogic

- Add support for Amlogic p200 & p201 Reference Designs
- Add Amlogic SoC information display
- Add support for the Libretech-AC AML-S805X-AC board
- Add Amlogic AXG reset compatible
- Add I2C support for Amlogic AXG
- Fix AXG PIN and BANK pinctrl definitions
- Fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
- Add initial support for Amlogic G12A SoC and U200 board
- Enable PHY_REALTEK for selected boards
- Fix Khadas VIM2 README
2019-04-24 12:26:25 -04:00
Stefan Roese
f2100f6f77 dm: core: Change platform specific translation-offset handling
Testing has shown that the current DM implementation of a platform /
board specific translation offset, as its needed for the SPL on MVEBU
platforms is buggy. The translation offset is confingured too late,
after the driver bind functions are run. This may result in incorrect
address translations. With the current implementation its not possible
to configure the offset earlier, as the DM code has not run at all.

This patch now removed the set_/get_translation_offset() calls and
moves the translation offset into the GD variable translation_offset.
This variable will get used when CONFIG_TRANSLATION_OFFSET is enabled.
This option is enabled only for MVEBU on ARM32 platforms, where its
currenty needed and configured in the SPL.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pierre Bourdon <delroth@gmail.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Pierre Bourdon <delroth@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
2019-04-23 20:26:43 -06:00
Lukas Auer
3a7c45f6a7 simple-bus: add DM_FLAG_PRE_RELOC flag to simple-bus driver
Boards such as qemu-riscv, which receive their device tree at runtime,
for example from QEMU or firmware, are unable to add the appropriate
device tree properties to make devices available pre relocation.
Instead, they must rely on the DM_FLAG_PRE_RELOC flag to be set for the
required drivers.

Add the DM_FLAG_PRE_RELOC flag to the simple-bus driver to make devices
under it with drivers that have set the flag as well available pre
relocation for these boards.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-23 20:26:43 -06:00
Fabien Parent
6fdb50c098 pinctrl: add driver for MT8516
Add Pinctrl driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
cd52c3253a clk: mediatek: add driver for MT8516
Add clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
[trini: Redo whitespace]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
fe913a8bb6 clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
b5096f1b6d mmc: mtk-sd: fix configuration option check
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.

This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-04-23 17:57:25 -04:00
Fabien Parent
a93326681d mmc: mtk-sd: add support for MT8516
Add config for handling MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:25 -04:00
Fabien Parent
ba077e5f74 mmc: mtk-sd: add source_cg clock support
Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:25 -04:00
Shawn Guo
1d5b5d2f8f net: add higmacv300 Ethernet driver for HiSilicon platform
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200.  It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Shawn Guo
f5e6c168c1 reset: add reset driver for HiSilicon platform
It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Thierry Reding
d94d9aa675 pci: Add boundary check for hose->regions
Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Philippe Reynes
4ac59e3381 led: bcm6858: allow to use this driver on ARCH_963158
Allow the led bcm6858 driver to be used on bcm63158.
They have the same led controller.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Christophe Kerello
c406a47431 mmc: stm32_sdmmc2: Fix r1b timeout issue
On response type r1b, if DTIME is not defined or too short,
the Datatimeout and DPSM flag occurs. Like the DPSM is
activated all next data transfer will be frozen.
To avoid this freeze:
    -The driver must define a DTIME on all r1b response type.
    -DTIME of SDMMC must be defined for alls stop transmission
     (for read and write request) even if MMC_RSP_BUSY is not set.
    -If busy timeout occur, an abort request must be sent to
     reinitialize the DPSM.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-23 15:42:28 +02:00
Patrick Delaunay
b611535238 mmc: stm32_sdmmc2: Update DT properties with v4.19 bindings
Some properties name has been updated:
  - st,dirpol becomes st,sig-dir
  - st,negedge becomes st,neg-edge
  - st,pin-ckin becomes st,use-ckin

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:42:23 +02:00
Patrice Chotard
6f41d1a17e mmc: arm_pl180_mmci: Sync compatible with kernel
Initially the compatible string was wrongly set to "st,stm32f4xx-sdio".
Use compatible string used by kernel instead and identify mmci variant
using "arm,primecell-periphid" property.

Currently, the DM part of mmci driver is only used by STM32 SoCs,
that's why the switch case gets only one entry. It will be populated
easily with new variant in the future.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:30 +02:00
Patrice Chotard
dd18df440a pinctrl: stm32: Add st,stm32f769-pinctrl compatible string
Due to DT kernel synchronisation, add new pinctrl compatible
string for stm32f769.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:25 +02:00
Jerome Brunet
912af8423f clk: meson: add g12a support
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
f5abfed8e9 clk: create meson directory and move related drivers
In order to support the Amlogic G12A clock controller,
re-architect the clock files into a meson directory.

No functionnal changes.

MAINTAINERS entry is also updated.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
f91121c794 pinctrl: meson: add g12a support
Add pinctrl support for the Amlogic G12A SoC, which is
very similar to the Amlogic AXG support but with an additionnal
drive-strength register bank.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Neil Armstrong
d0a9b82b75 regmap: fix regmap_read_poll_timeout warning about sandbox_timer_add_offset
When fixing sandbox test for regmap_read_poll_timeout(), the
sandbox_timer_add_offset was introduced but only defined in sandbox code
thus generating warnings when used out of sandbox :

include/regmap.h:289:2: note: in expansion of macro 'regmap_read_poll_timeout_test'
regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/meson_spifc.c:169:8: note: in expansion of macro 'regmap_read_poll_timeout'
ret = regmap_read_poll_timeout(spifc->regmap, REG_SLAVE, data,
        ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/meson_spifc.c: In function 'meson_spifc_txrx':
include/regmap.h:277:4: warning: implicit declaration of function 'sandbox_timer_add_offset' [-Wimplicit-function-declaration]

This fix adds a timer_test_add_offset() only defined in sandbox, and
renames the previous sandbox_timer_add_offset() to it.

Cc: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
Fixes: df9cf1cc08 ("test: dm: regmap: Fix the long test delay")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 11:17:15 +02:00
Philippe Reynes
d00c6a2d56 led: add initial support for bcm6858
The driver add the support of the led IP on bcm6858.
This led IP can drive up to 32 leds, and can handle
blinking.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-22 18:13:24 -04:00