Commit graph

5330 commits

Author SHA1 Message Date
Hans de Goede
e79c7c8810 sunxi: When we've both mmc0 and mmc2, detect from which one we're booting
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.

When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Maxime Ripard
8a6564dacb ARM: sunxi: Add basic A31 support
Add a new sun6i machine that supports UART and MMC.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
		around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Maxime Ripard
7711539734 ARM: sun6i: Setup the A31 UART0 muxing
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
[wens@csie.org: reorder #ifs by SUN?I]
[wens@csie.org: replace magic numbers with GPIO definitions]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
ba1e40fdd3 ARM: sun6i: Define UART0 pins for A31
UART0 is the default debug/console UART on the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
1d1bd42eb0 ARM: sunxi-mmc: Add mmc support for sun6i / A31
The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
		rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Chen-Yu Tsai
14177e47e8 ARM: sun6i: Add clock support
This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Oliver Schinagl
174deb768c ARM: sun6i: Add support for the power reset control module found on the A31
The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
		supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Oliver Schinagl
93ce1e9dad ARM: sun6i: Add base address for the new controllers in A31
A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Chen-Yu Tsai
ea520947b1 ARM: sunxi: Use macro values for setting UART GPIO pull-ups
We have already defined macros for pull-up/down values in the
GPIO header. Use them instead of magic numbers when configuring
the UART pins.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Masahiro Yamada
d064cbffff dm: serial: use Driver Model for UniPhier serial driver
This commit converts UniPhier on-chip serial driver to driver model.

Since UniPhier SoCs do not have Device Tree support, some board files
should be added under arch/arm/cpu/armv7/uniphier/ph1-*/ directories.
(Device Tree support for UniPhier platform is still under way.)

Now the base address and master clock frequency are passed from
platform data, so CONFIG_SYS_UNIPHIER_SERIAL_BASE* and
CONFIG_SYS_UNIPHIER_UART_CLK should be removed.

Tested on UniPhier PH1-LD4 ref board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-23 21:43:09 -06:00
Simon Glass
e98a03ca68 dm: x86: Convert coreboot serial to use driver model
This makes use of the existing device tree node to use driver model
for the serial console.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:45 -06:00
Simon Glass
d1259c9f5f dm: x86: dts: Add additional info to the serial port node
Add more information so that U-Boot can find the address of the serial port.
Also fix the reg-shift value.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
c15b0b86d1 dm: x86: Add a gpio header for coreboot
This code doesn't follow the normal approach of having its arch-specific
definitions in an arch-specific directory. Add a new arch-specific file
and make use of it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
5dbcaa2128 dm: x86: Support pre-reloc malloc()
Add support for this by reserving a block of memory below global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
fbd7282426 dm: x86: Zero global data before board_init_f()
To permit information to be passed from the early U-Boot code to
board_init_f() we cannot zero the global_data in board_init_f(). Instead
zero it in the start-up code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
9c284ffd93 dm: x86: Remove ebp assembler warning in zimage.c
This code generates warnings with recent gcc versions. We really don't need
the clobber specification, so just drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:45:28 -06:00
Simon Glass
2d91a9772c dm: dts: Move omap device tree includes to correct place
These ended up in arch/arm/dts/dt-bindings temporarily, but in fact the
correct place is now include/dt-bindings. Move them to be consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-23 19:30:51 -06:00
Simon Glass
b3f4ca1135 dm: omap3: Move to driver model for GPIO and serial
Adjust the configuration for the am33xx boards, including beagleboard,
to use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
2014-10-23 19:29:07 -06:00
Simon Glass
4119e06dd8 dm: am33xx: Provide platform data for serial
Provide suitable platform data for am33xx boards, so that these boards can
use driver model for serial.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-10-23 19:29:07 -06:00
Simon Glass
d12010b099 dm: am33xx: Provide platform data for GPIOs
Provide suitable platform data for am33xx boards, so that these boards can
use driver model for GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-10-23 19:29:07 -06:00
Simon Glass
5915a2ad0d dm: omap: gpio: Support driver model
Add driver model support to this driver, while retaining support for the
legacy system. Driver model GPIO support is enabled with CONFIG_DM_GPIO
as usual.

Since gpio_is_valid() no longer exists, we can use the -EINVAL error
returned from gpio_request().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-10-23 19:29:07 -06:00
Simon Glass
2539f3926c dm: dts: omap: Select correct console for beaglebone
Select serial0 as the console.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
2014-10-23 19:29:07 -06:00
Tom Rini
03a3536c7b Merge branch 'master' of git://git.denx.de/u-boot-tegra 2014-10-23 14:05:34 -04:00
Masahiro Yamada
7bfd5ee117 mips: enable CONFIG_USE_PRIVATE_LIBGCC by default
Without the private libgcc, we need a full multilib toolchain with
different libgcc or multiple toolchains to build all BE/LE and
hard-float/soft-float variants of MIPS boards.  That is not feasible.

This commit allows us to build all the MIPS boards with a single
kernel.org toolchain:

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_mips-linux.tar.xz

This change sounds reasonable for most users.  If necessary,
you can disable this option via "make menuconfig" or friends.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2014-10-23 13:19:15 -04:00
Masahiro Yamada
45ccec8f29 kconfig: move CONFIG_USE_PRIVATE_LIBGCC to Kconfig
The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86.
Those architectures should "select" HAVE_PRIVATE_LIBGCC and
CONFIG_USE_PRIVATE_LIBGCC should depend on it.

Currently, this option is enabled on Tegra boards and x86 architecture.
Move the definition from header files to Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
2014-10-23 13:19:09 -04:00
Masahiro Yamada
dd43fa22de x86: set CONFIG_USE_PRIVATE_LIBGCC to y
The motivation of this commit is to change CONFIG_USE_PRIVATE_LIBGCC
to a boolean macro so we can move it to Kconfig.

In the current implementation, there are two forms of syntax
for this macro:

  - CONFIG_USE_PRIVATE_LIBGCC=y
  - CONFIG_USE_PRIVATE_LIBGCC=path/to/private/libgcc

The latter is only used by x86 architecture.
With a little bit refactoring, it can be converted to the former.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-23 13:19:04 -04:00
Igor Grinberg
b5ff205cdb omap3/am33xx: mux: fix several checkpatch issues
Fix the following checkpatch issues:

CHECK: No space is necessary after a cast
\#39: FILE: arch/arm/include/asm/arch-am33xx/mux.h:39:
+#define PAD_CTRL_BASE  0x800
+#define OFFSET(x)      (unsigned int) (&((struct pad_signals *) \

CHECK: Avoid CamelCase: <CONTROL_PADCONF_JTAG_nTRST>
\#284: FILE: arch/arm/include/asm/arch-omap3/mux.h:284:
+#define CONTROL_PADCONF_JTAG_nTRST     0x0A1C

ERROR: space required after that ',' (ctx:VxV)
\#446: FILE: arch/arm/include/asm/arch-omap3/mux.h:446:
+#define MUX_VAL(OFFSET,VALUE)\
                       ^
Cc: Raphael Assenat <raph@8d.com>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Stefan Roese <sr@denx.de>
2014-10-23 11:53:02 -04:00
Igor Grinberg
52edc87740 omap3: Kconfig: fix the cm-t35 board option prompt
The cm-t35 board support covers both cm-t3530 and cm-t3730 boards.
Mention both boards in the Kconfig option prompt.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2014-10-23 11:53:01 -04:00
Hao Zhang
26459488b7 ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr
Add ddr3 commands:

test <start_addr in hex> <end_addr in hex> - test DDR from start\n
	address to end address\n
ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n
	compare DDR data of (size) bytes from start address to end
	address\n
ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n
	in DDR data at <addr>, the command will read a 32-bit data\n
	from <addr>, and write (data ^ bit_err) back to <addr>\n

Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used
for ddr3 commands and for now it's not needed any more.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Vitaly Andrianov
89f44bb0ce keystone2: ecc: add ddr3 error detection and correction support
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.

By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.

An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Vitaly Andrianov
079da2d514 ARM: keystone: msmc: extend functionality of SES
Add functions to set/get SES PMAX values of Pivilege ID pair.
Also add msmc module definitions.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
e165b1d34c dma: ti-edma3: introduce edma3 driver
The EDMA3 controller’s primary purpose is to service data transfers
that you program between two memory-mapped slave endpoints on the device.

Typical usage includes, but is not limited to the following:
- Servicing software-driven paging transfers (e.g., transfers from external
  memory, such as SDRAM to internal device memory, such as DSP L2 SRAM)
- Servicing event-driven peripherals, such as a serial port
- Performing sorting or sub-frame extraction of various data structures
- Offloading data transfers from the main device DSP(s)
- See the device-specific data manual for specific peripherals that are
  accessible via the EDMA3 controller

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
69a3b81141 ARM: keystone: clock: add support for K2E SoCs
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
ff11c7697c net: keystone_net: add Keystone2 K2E SoC support
The Keystone2 Edison SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2E SoCs.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
3c61502aad net: keystone_serdes: add keystone K2E SoC support
Keystone2 Edison SoC uses the same keystone SerDes driver.
This patch adds support for K2E SoCs.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
2162faaf58 ARM: keystone2: keysonte_nav: add support for K2E SoC
Keystone2 Edison SoC uses the same keystone navigator, but
uses different NETCP PktDMA definitions. This patch adds
required definitions.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:29 -04:00
Khoronzhuk, Ivan
3fe93623cc net: keystone_net: register eth PHYs on MDIO bus
As MDIO bus has been added we can register PHYs with it.
After registration, the PHY driver will be probed according to the
hardware on board.

Startup PHY at the ethernet open.

Use phy_startup() instead of keystone_get_link_status() when eth open,
as it verifies PHY link inside and SGMII link is checked before.

For K2HK evm PHY configuration at init was absent, so don't enable
phy config at init for k2hk evm.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Hao Zhang
92a16c81f5 soc: keystone_serdes: generalize to be used by other sub systems
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Hao Zhang
95f74dad91 soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Khoronzhuk, Ivan
a43febde44 soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.

Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:28 -04:00
Vitaly Andrianov
f077226610 net: keystone_net: increase MDIO clock frequency
With MAC_PHY sgmii configuration, u-boot checks PHY link status before
sending each packet. Increasing MDIO frequency increases overall tftp
speed. We set it to maximum 2.5MHz.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Khoronzhuk, Ivan
0935cac685 net: keystone_net: move header file from arch to ti-common
The header file for the driver should be in correct place.
So move it to "arch/arm/include/asm/ti-common/keystone_net.h"
and correct driver's external dependencies. At the same time
align and correct some definitions.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Khoronzhuk, Ivan
e3114c9a06 net: keystone_net: add support for NETCP v1.5
Currently the network driver is used only by k2hk evm board.
The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e
contain NETCP v1.5. So driver should be able to work with such kind
of NETCP. This commit adds this opportunity. The main difference in
masks and some registers, the logic is the same, so only definitions
should be changed. To differentiate between versions add KS2_NETCP_V1_0
and KS2_NETCP_V1_5. Also remove unused and no more needed defines.

The port number is specific for each board so move this parameter to
configuration.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
b2cfe32278 net: keystone_net: remove SoC specific emac_regs structure
This patch removes K2HK SOC specifc emac_regs structure, it uses
soc specific register offset to keep the network driver common across
all the Keystone II EVMs.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
345af53456 keystone2: k2l-evm: add board support
This patch adds Keystone II Lammar (K2L) EVM board support.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
b66604fb66 keystone2: enable OSR clock domain for K2L SoC
This patches enables the On-chip Shared Ram clock domain for K2L SoC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
5ec66b140a ARM: keystone2: spl: move board specific code
The initialization of PLLs is a part of board specific code, so
move it appropriate places.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
bc45d5729f keystone2: msmc: add MSMC cache coherency support for K2L SOC
This patch adds Keystone II Lamar (K2L) SoC specific definitions
to support MSMC cache coherency.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:05 -04:00
Hao Zhang
61d122583f keystone2: clock: add K2L clock definitions and commands
This patch adds clock definitions and commands to support Keystone II
K2L SOC.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Hao Zhang
c4995a8282 ARM: keystone2: add K2L device hardware definitions
This patch adds hardware definitions specific to Keystone II
Lamar (K2L) SoC.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Khoronzhuk, Ivan
529ce1eedf ARM: cmd_clock: generalize command usage description
The usage description of commands refers to headers of sources,
that is not correct. This patch is intended to fix it.
Also generalize code in order to reduce SoC dependent #ifdefs.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
WingMan Kwok
bc0e8d7c5d keystone: usb: add support of usb xhci
Add support of usb xhci. xHCI controls all USB speeds of the Host
mode, that is, the SS through the SS PHY, as well as the HS, FS, and
LS through the USB2 PHY. xHCI replaces and supersedes all previous
host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not
backwards compatible with any of them. The USB3SS’s USB Controller is
fully compliant with xHC.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Khoronzhuk, Ivan
9ea9021ac4 dma: keystone_nav: generalize driver usage
The keystone_nav driver is general driver intended to be used for
working with queue manager and pktdma for different IPs like NETCP,
AIF, FFTC, etc. So the it's API shouldn't be named like it works only
with one of them, it should be general names. The names with prefix
like netcp_* rather do for drivers/net/keystone_net.c driver. So it's
good to generalize this driver to be used for different IP's and
delete confusion with real NETCP driver.

The current netcp_* functions of keystone navigator can be used for
other settings of pktdma, not only for NETCP. The API of this driver
is used by the keystone_net driver to work with NETCP, so net driver
also should be corrected. For convenience collect pkdma
configurations in drivers/dma/keystone_nav_cfg.c.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Khoronzhuk, Ivan
ef4547176d dma: keystone_nav: move keystone_nav driver to driver/dma/
The keystone_nav is used by drivers/net/keystone_net.c driver to
send and receive packets, but currently it's placed at keystone
arch sources. So it should be in the drivers directory also.
It's separate driver that can be used for sending and receiving
pktdma packets by others drivers also.

This patch just move this driver to appropriate directory and
doesn't add any functional changes.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Khoronzhuk, Ivan
ed948e2959 keystone2: keystone_nav: don't use hard addresses in netcp_pktdma
Use definitions in netcp_pktdma instead direct addresses.
The definitions can be set specifically for SoC, so there
is no reason to check SoC type while initialization.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Khoronzhuk, Ivan
afa479cf66 keystone2: keystone_nav: don't use hard addresses in qm_config
Use definitions in qm_config. The definitions can be set specifically
for SoC, so there is no reason to check SoC type while initialization.

Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-10-23 11:27:04 -04:00
Stefan Roese
1721fe6966 arm: kirkwood: Remove some dead code from cpu.c
All those functions removed with this patch are not accessed at all. So lets
remove them.

Signed-off-by: Stefan Roese <sr@denx.de>
2014-10-23 09:59:21 -04:00
Stefan Roese
a488483174 arm: armada-xp: Add basic support for the maxBCM board
The maxBCM board is equipped with the Marvell Armada-XP MV78460 SoC. It
integrates an SPI NOR flash and an Marvell 88E6185 switch.

Signed-off-by: Stefan Roese <sr@denx.de>
2014-10-23 09:59:21 -04:00
Stefan Roese
dd580801aa arm: armada-xp: Add basic support for the Marvell DB-MV784MP-GP board
This patch adds basic support for the Marvell DB-MV784MP-GP evaulation
board. This is the first board that uses the recently created
Armada XP 78460 SoC support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
2014-10-23 09:59:21 -04:00
Stefan Roese
41e5ee54e3 arm: armada-xp: Add basic support for Marvell Armada XP SoC
This basic support for the Marvell Armada XP is base on the existing kirkwood
support. Which has been generatized by moving some common files into
common marvell locations.

This is in preparation for the upcoming Armada XP MV78460 support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
2014-10-23 09:59:21 -04:00
Stefan Roese
96c5f0816a arm: kirkwood: Change naming of dram functions from km_foo() to mvebu_foo()
Additionally the SDRAM address decoding register address is not hard coded
in the C code any more. A define is introduced for this base address.

This makes is possible to use those gpio functions from other MVEBU SoC's
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:21 -04:00
Stefan Roese
4fd7717e8e spi: kirkwood_spi.c: Change KW_SPI_BASE to MVEBU_SPI_BASE
This makes is possible to use this SPI driver from other MVEBU SoC's as well.
As the upcoming Armada XP support will do.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:21 -04:00
Stefan Roese
d5c5132f87 arm: marvell: Extract kirkwood gpio functions into new common file gpio.c
This makes is possible to use those gpio functions from other MVEBU SoC's as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:21 -04:00
Stefan Roese
24c04977fa arm: mvebu: Add common mbus functions to use on Marvell SoCs
These mbus functions are ported from Barebox. The Barebox version is
ported from Linux. These functions will be first used by the upcoming
Armada XP support. Later other Marvell SoC's will be adopted to use
these functions as well (Kirkwood, Orion).

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
2014-10-23 09:59:20 -04:00
Stefan Roese
22700dc6fb arm: marvell: Rework timer.c to make it usable for other MVEBU platforms
This patch does the following:
- Rename defines and registers to not use kirkwood
- Remove unused defines
- Use clrsetbits() accessor functions
- Coding style cleanup
- Clear 25MHZ bit in timer controller register init for Armada XP

There is no functional change for kirkwood. At least not intentionally.

This will be used by the upcoming Armada XP support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:20 -04:00
Stefan Roese
3e972cb9ba arm: marvell: Move arch-kirkwood/spi.h to arch-mvebu/spi.h
This move makes it possible to use this kirkwood SPI driver from other
MVEBU platforms as well. This will be used by the upcoming Armada XP
support.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:20 -04:00
Stefan Roese
3dc23f7852 arm: marvell: Move arch/kirkwood.h to arch/soc.h
This move makes is possible to use this header not only from kirkwood
platforms but from all Marvell mvebu platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:59:20 -04:00
Stefan Roese
d80cca29fe arm: kirkwood: Move some SoC files into new arch/arm/mvebu-common
By moving some kirkwood files into a Marvell common directory, those files
can be used by other Marvell platforms as well. The name mvebu is taken
from the Linux kernel source tree. It has been chosen there to represent
the SoC's from the Marvell EBU (Engineering Business Unit). Those SoC's
currently are:

Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x

This will be used by the upcoming Armada XP (MV78460) platform support.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Luka Perkov <luka@openwrt.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
2014-10-23 09:58:41 -04:00
Tom Rini
dee8abcd80 Merge git://git.denx.de/u-boot-x86 2014-10-23 06:54:03 -04:00
Simon Glass
6ddc4fd822 x86: Add device tree information for Chrome OS EC
Add the required node describing how to find the EC on link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:32 -06:00
Stephen Warren
4f80a06df3 ARM: rpi_b: query internal MAC address from firmware
The built-in SMSC 95xx chip doesn't know its own MAC address. Instead,
we must query it from the VC firmware; it's probably encoded in fuses
on the BCM2835.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-10-22 22:02:08 +02:00
Tom Rini
68e80fdda1 Merge git://git.denx.de/u-boot-dm 2014-10-22 13:51:45 -04:00
Simon Glass
41e98e011d dm: rpi: Convert GPIO driver to driver model
Convert the BCM2835 GPIO driver to use driver model, and switch over
Raspberry Pi to use this, since it is the only board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2014-10-22 10:36:57 -06:00
Simon Glass
c6f3f32356 dm: imx: i2c: Use gpio_request() to request GPIOs
GPIOs should be requested before use. Without this, driver model will
not permit the GPIO to be used.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2014-10-22 10:36:55 -06:00
Simon Glass
edbf8b4f8c imx: Add error checking to setup_i2c()
Since this function can fail, check its return value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-10-22 10:36:55 -06:00
Simon Glass
fda6fac39b dm: tegra: spi: Convert to driver model
This converts the Tegra SPI drivers to use driver model. This is tested
on:

- Tegra20 - trimslice
- Tegra30 - beaver
- Tegra124 - dalmore

(not tested on Tegra124)

Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:52 -06:00
Simon Glass
d2f60f9332 dm: tegra: dts: Add aliases for spi on tegra30 boards
All boards with a SPI interface have a suitable spi alias except the tegra30
boards. Add these missing aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:52 -06:00
Simon Glass
b6c2956def dm: sf: sandbox: Convert SPI flash driver to driver model
Convert sandbox's spi flash emulation driver to use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:51 -06:00
Simon Glass
0043b1faa7 exynos: universal_c210: Move to driver model soft_spi
Adjust this board to use the driver model soft_spi implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:49 -06:00
Simon Glass
73186c9460 dm: exynos: Convert SPI to driver model
Move the exynos SPI driver over to driver model. This removes quite a bit
of boilerplate from the driver, although it adds some for driver model.

A few device tree additions are needed to make the SPI flash available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:49 -06:00
Simon Glass
49b5d6e6e2 dm: sandbox: spi: Move to driver model
Adjust the sandbox SPI driver to support driver model and move sandbox over
to driver model for SPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-10-22 10:36:48 -06:00
Simon Glass
0b304a2494 sandbox: dts: Add a SPI device and cros_ec device
Add a SPI device which can be used for testing SPI flash features in
sandbox.

Also add a cros_ec device since with driver model the Chrome OS EC
emulation will not otherwise be available.

Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:45 -06:00
Simon Glass
9208fffebc dm: exynos: Mark exynos5 console as pre-reloc
We will need the console before relocation, so mark it that way.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:44 -06:00
Simon Glass
b8809e60cd dm: exynos: gpio: Convert to driver model
Convert the exynos GPIO driver to driver model. This implements the generic
GPIO interface but not the extra Exynos-specific functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:36 -06:00
Simon Glass
7f1961018c dm: exynos: Make sure that GPIOs are requested
With driver model GPIOs must be requested before use. Make sure this is
done correctly.

(Note that the soft SPI part of universal is omitted, since this driver
is about to be replaced with a driver-model-aware version)

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:33 -06:00
Simon Glass
903fd79564 dm: exynos: Tidy up GPIO headers
The wrong header is being included, thus requiring the code to re-declare
the generic GPIO interface in each GPIO header.

Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:18 -06:00
Simon Glass
3b7a326c95 dm: exynos: Add pinctrl settings for s5p_goni
These describe the GPIOs in enough detail for U-Boot's GPIO driver to
operate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:04 -06:00
Simon Glass
3a4ed03cde dm: exynos: Add pinctrl settings for smdkc100
These describe the GPIOs in enough detail for U-Boot's GPIO driver to
operate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:36:00 -06:00
Simon Glass
c6b0b09032 dm: exynos: dts: Adjust device tree files for U-Boot
The pinctrl bindings used by Linux are an incomplete description of the
hardware. It is possible in most cases to determine the register address
of each, but not in all cases. By adding an additional property we can
fix this, and avoid adding a table to U-Boot for every single Exynos
SOC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:35:57 -06:00
Simon Glass
41678484b3 dm: exynos: dts: Remove unused pinctrl information to save space
We don't include the pinctrl functions for U-Boot as they use up quite
a bit of space and are not used.

We could instead perhaps eliminate this material with fdtgrep, but so far
this tool has not made it to upstream.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:34:12 -06:00
Simon Glass
dd54739dc4 dm: exynos: Bring in pinctrl dts files from Linux kernel
Bring in required device tree files for pinctrl from Linux v3.14. These
are initially unchanged and have a number of pieces not needed by U-Boot.

Note that exynos5420 is renamed to exynos54xx here since we want to
support exynos5422 also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:34:08 -06:00
Simon Glass
2fdd7d9e1a dm: exynos: dts: Convert /include/ to #include
We should be consistent about this. The kernel has moved to #include
which breaks error reporting to some extent but does allow us to include
binding files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 10:34:00 -06:00
Marcel Ziswiler
9aafef4f36 tegra: apalis_t30: master revamp
Update Apalis T30 as per the following commits

c369139234
tegra: dts: Add serial port details

461be2f96e
kconfig: remove redundant "string" type in arch and board Kconfigs

f1ef2b6233
kconfig: move CONFIG_DEFAULT_DEVICE_TREE to kconfig

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-10-22 09:30:55 -07:00
Marcel Ziswiler
f38aaa28be tegra: dts: colibri_t30 add serial port details
Add missing chosen stdout-path device tree node. This got missed by
commit

c369139234
tegra: dts: Add serial port details

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-10-22 09:30:55 -07:00
Marcel Ziswiler
8c33ba7b1d ARM: tegra: Use mem size from MC in combination with get_ram_size()
On popular request this now completes the Warren's work started for
TK1:

aeb3fcb359
ARM: tegra: Use mem size from MC rather than ODMDATA

In addition to the move of using the Tegra memory controller (MC)
register rather than ODMDATA for T20, T30 and T114 as well it further
uses the generic get_ram_size() function (see "common/memsize.c")
<supposed to be used in each and every U-Boot port>TM. Added benefit is
that it should <catch 99% of hardware related (i. e. reliably
reproducible) memory errors> as well.

Thoroughly tested on the various Toradex line of Tegra modules
available which unfortunately does not include T114 and T124 (yet at
least) plus on the Jetson TK1.

Based-on-work-by: Stephen Warren <swarren@nvidia.com>
Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-10-22 09:30:55 -07:00
Marcel Ziswiler
bf78b2717d arm: tegra: initial support for apalis t30
This patch adds board support for the Toradex Apalis T30 a computer on
module which can be used on different carrier boards.

For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.

The following functionality is working so far:
- eMMC boot and environment storage
- Gigabit Ethernet (once Thierry's PCIe as well as my E1000 resp. i210
  fixes hit mainline)
- MMC/SD cards (both 8-bit as well as 4-bit slot)
- USB client/host (dual role port as client e.g. for DFU/UMS, other two
  ports as host)

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-10-22 09:30:54 -07:00
Bin Meng
35d4fed320 x86: Fix GDT limit in start16.S
GDT limit should be one less than an integral multiple of eight.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-22 09:03:07 -06:00
Bin Meng
fb00601ed6 x86: Fix rom version build with CONFIG_X86_RESET_VECTOR
When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to
pull them into the final linking process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-22 09:03:07 -06:00
Simon Glass
97d1e0c850 x86: Allow cmdline setup in setup_zimage() to be optional
If we are passing this using the device tree then we may not want to
set this up here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 09:03:05 -06:00
Simon Glass
0d0ba59ccd x86: Rewrite bootm.c to make it similar to ARM
The x86 bootm code is quite special, and geared to zimage. Adjust it
to support device tree and make it more like the ARM code, with
separate bootm stages and functions for each stage.

Create a function announce_and_cleanup() to handle printing the
"Starting kernel ..." message and put it in bootm so it is in one
place and can be used by any loading code. Also move the
board_final_cleanup() function into bootm.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 09:03:05 -06:00