Commit graph

18 commits

Author SHA1 Message Date
Priyanka Jain
5193405a16 board: freescale: ls2080ardb: Enable SD interface for RevF board
LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
which needs to be programmed to enable high speed SD interface
by setting GPIO4_10 output to zero.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23 09:12:26 -07:00
Santan Kumar
54ad7b5ab8 board: freescale: ls2080a/ls2088a: Enable PPA
Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:27:58 -07:00
Udit Agarwal
a8c6fd4ec1 armv8: LS2080A: Move sec_init to board_init
Moves sec_init to board_init rather than in misc_init function beacuse
PPA will be initialised in board_init function and for PPA validation
sec_init has to be done prior to PPA init.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 08:58:46 -07:00
York Sun
4961eafc25 armv8: layerscape: Update early MMU for DDR after initialization
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
York Sun
36cc0de0b9 armv8: layerscape: Rewrite memory reservation
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-03-14 08:44:03 -07:00
Alexander Graf
215b1fb9fa ls2080ardb: Reserve DP-DDR RAM
The DP-DDR shouldn't be exposed as conventional memory to an OS, so let's
rather claim it's a reserved region in the EFI memory map

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-11-17 14:18:55 +01:00
Alexander Graf
b7b8410a8f ls2080: Exit dpaa only right before exiting U-Boot
On ls2080 we have a separate network fabric component which we need to
shut down before we enter Linux (or any other OS). Along with that also
comes configuration of the fabric using a description file.

Today we always stop and configure the fabric in the boot script and
(again) exit it on device tree generation. This works ok for the normal
booti case, but with bootefi the payload we're running may still want to
access the network.

So let's add a new fsl_mc command that defers configuration and stopping
the hardware to when we actually exit U-Boot, so that we can still use
the fabric from an EFI payload.

For existing boot scripts, nothing should change with this patch.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
[agraf: Fix x86 build]
2016-11-17 14:18:55 +01:00
Sriram Dash
a5c289b9bc usb: fsl: Rename fdt_fixup_dr_usb
The function fdt_fixup_dr_usb is specific to fsl/nxp. So,
make the function name explicit and rename fdt_fixup_dr_usb
into fsl_fdt_fixup_dr_usb.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
2016-09-27 23:30:27 +02:00
York Sun
b63a950629 armv8: ls2080a: Remove debug server support
Debug server feature has been dropped from roadmap.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-09-14 14:07:19 -07:00
Sriram Dash
ef53b8c4ce usb: xhci: fsl: Add workaround for USB erratum A008751
This patch is doing the following:
1. Implementing the errata for LS2080.
2. Adding fixup for fdt for LS2080.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-06-13 15:16:46 +02:00
York Sun
931e8751af board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not defined
U-Boot should continue to work without management complex (MC).
Fix compiling errors and warnings.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03 14:12:48 -07:00
York Sun
3c1d218a1d armv8: LS2080A: Consolidate LS2080A and LS2085A
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2016-04-06 10:26:46 -07:00
Rai Harninder
ed2530d096 armv8/ls2080ardb: Enable VID support
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.

Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:24 -07:00
Saksham Jain
fcfdb6d580 armv8: ls2080rdb: ls2080qds: Add secure boot support
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).

Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-29 08:46:20 -07:00
Stuart Yoder
e91f1deca5 armv8: ls2080a: Update fdt path for fsl-mc node
The fsl-mc node has been moved under /soc, so update
the path references accordingly.  Backwards compatibility
is retained for /fsl-mc.

Delete backwards compatibility for the completely obsolete
/fsl,dprc@0.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-24 11:43:31 -07:00
Shaohui Xie
abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
York Sun
c04921414c armv8: fsl-layerscale: Rewrite reserving memory for MC and debug server
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:33 +08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Renamed from board/freescale/ls2085ardb/ls2085ardb.c (Browse further)