Commit graph

1588 commits

Author SHA1 Message Date
Tom Rini
9809ccdd4c Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2015-09-02 11:30:46 -04:00
Tom Rini
0ffadab1b9 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-09-02 10:39:28 -04:00
Peng Fan
e7d3b21bb7 imx: mx6slevk: add SPL support
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.

Boot Log:

U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)

CPU:   Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:13 +02:00
Peng Fan
f2ff834365 imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.

Initialize ddr_type for different boards which enable SPL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
0d4cdb5609 imx: mx6ul_14x14_evk add ENET support
Add enet support for mx6ul_14x14_evk board:
1. add pinmux settings
2. implement board_eth_init
3. implement board_phy_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
2015-09-02 15:34:11 +02:00
Peng Fan
6d97dc10a8 imx: clock support enet2 anatop clock support
To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:29:14 +02:00
Zhuoyu Zhang
03c22449c5 arm/ls102xa:add hwconfig setting to support disable unused devices
DEVDISRn registers provides a mechanism for gating clocks of IP blocks
that are not used. Here we implement hwconfig option to allow users
to disable unused peripherals on the board.

For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts,
User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma"
in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to
save more power.

Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:49:20 -05:00
York Sun
ec93af0dec armv8/ls2085a_emu: Drop DDR3 emulation target
The emulator with DDR3 model was used during model bringup. DDR4
controllers are used with ls2085a. Drop the DDR4 target defconfig
and enable DDR4 in ls2085a_emu_defconfig.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01 21:39:21 -05:00
Claudiu Manoil
ebe4c1e646 ls102xa: etsec: Use proper settings for BE BDs
Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:39:03 -05:00
Prabhakar Kushwaha
cf7ee6c4e3 armv8: ls2085qds: Add support of X-QSGMII-16PORT riser card
The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
interfaces implemented in PCIe form factor board.
It supports followings
 - Card can operate with up to 4 QSGMII lane simultaneously
 - Card can operate with up to 8 SGMII lane simultaneously

Add support of X-QSGMII-16PORT riser card.
This patch also take care of back-ward compatiblity with old SGMII rise cards
used on LS2085QDS Platform.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:38:46 -05:00
Priyanka Jain
7fb79e6552 armv8/ls2085aqds: enable 32KHz rtc output
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:37:42 -05:00
Shengzhou Liu
47deb4b4a9 powerpc/t1023rdb: change default core frequency to 1200MHz
Per new requirement, change default core frequency
from previous 1400MHz to 1200MHz to save power.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 20:58:58 -05:00
York Sun
293194c8be powerpc/defconfig: Rename defconfig file for T1040QDS/T1024QDS DDR4 targets
Previously the DDR4 targets were named with _D4. Rename them with
_DDR4 for easy identification.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01 20:42:54 -05:00
Peng Fan
125914d4be fsl: common: pfuze: no use original pfuze code if DM_PMIC
If enable DM PMIC and REGULATOR, we should not use original power
framework. So need to comment out the pfuze code for original power
framework, when CONFIG_DM_PMIC_PFUZE100 defined.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-12 11:05:11 +02:00
Alison Wang
8f0c7cbb0d armv7/ls1021a: allow OCRAM access permission as R/W in SPL
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:37 -07:00
chenhui zhao
933db81c04 armv7/ls1021atwr: program the regulator for deep sleep
Program the external regulator to switch off voltage in deep sleep.

Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tang Yuantian
99e1bd4241 armv7/ls1021atwr: added deep sleep support in uboot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:36 -07:00
Tom Rini
7a1af7a79b Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-08-02 07:40:37 -04:00
Peng Fan
f0ff57b0b2 imx: mx6ul_14x14_evk add basic board support
1. Add USDHC, I2C, UART, 74LV, USB, QSPI support.
2. Support SPL
3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default
   supports sd for usdhc2, but can do hardware rework to make usdhc2 support
   emmc.

Boot Log:
U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59)
reading u-boot.img
reading u-boot.img

U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800)

CPU:   Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C)CPU:   Thermal invalid data, fuse: 0x0
 - invalid sensor device
 Reset cause: POR
 Board: MX6UL 14x14 EVK
 I2C:   ready
 DRAM:  512 MiB
 MMC:   FSL_SDHC: 0, FSL_SDHC: 1
 *** Warning - bad CRC, using default environment

 In:    serial
 Out:   serial
 Err:   serial
 Net:   CPU Net Initialization Failed
 No ethernet found.
 Hit any key to stop autoboot:  0

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Peng Fan
361b715bbf imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
   and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.

Build target: mx6qpsabreauto_config

Boot Log:
U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)

CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
PMIC:  PFUZE100 ID=0x10
Flash: 32 MiB
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

No panel detected: default to HDMI
Display: HDMI (1024x768)
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

Note:
In this patch, we still add a new config mx6qpsabreauto_config,
since SPL is not supported now, and IMX_CONFIG is needed at
build time, so add this config. Future, when SPL is converted,
this config can be removed.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-08-02 10:47:52 +02:00
Peng Fan
e6fc8995d6 imx: mx6sabresd/sabreauto runtime setting fdt_file
Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.

Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2015-08-02 10:47:05 +02:00
Priyanka Jain
f2af1c37a0 powerpc/T104xRDB: Remove vbank check redundant code
sw variable in checkboard function is storing vbank value
which can only take 3-bit value.
So check of sw value for if greater than 7 is redundant.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:56:11 -07:00
Shengzhou Liu
e04dd12bf1 powerpc/t1023rdb: eMMC boot without external SD card
eMMC has no CD and WP pins, it needs to add board-specific
board_mmc_getcd() and board_mmc_getwp() in SPL to support
eMMC boot without external SD card inserted.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:19 -07:00
Shengzhou Liu
ff7ea2d18b powerpc/t1023rdb: add support for T1023RDB RevC
Add support for NOR flash and GPIO/I2C switch control on RevC.
- NOR support
- bank0/bank4 switch
- SD/eMMC switch
- board version

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
73cc2f50eb powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040
Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Aneesh Bansal
467a40dfe3 powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.

In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31 08:50:18 -07:00
Priyanka Jain
fa9ccff835 powerpc/t104x, t102x: Update CPC debug register value in PBI commands
Update PBI command in pbi_cfg files to keep register bit
to default reset value while configuring CPC
as SRAM

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
Shaohui Xie
f57709ab18 powerpc/t4rdb: fix cpld reset altbank
cpld reset altbank should always reset to bank4 no matter what
current bank is.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
Ying Zhang
01a6113d2a powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue
Because the function ft_board_setup() delete the USB2 device node, it
leads to can't find the device node and hung up.

In fact only P1020RDB needs to delete the USB2 node, this patch fixes
this issue.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:15 -07:00
gaurav rana
e622d9ed3b powerpc/T104xD4: Add Secure boot support for T104xD4RDB platforms
defconfig files are added and SFP version for these platforms
is updated.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:41:14 -07:00
Priyanka Jain
4b6067ae9d powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
    T1040D4RDB is re-designed T1040RDB board with following changes :
    - Support of DDR4 memory
    - Support of 0x66 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 1 SGMII on DTSEC3
    - Support of QE-TDM

    Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
    SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
    - Support of DDR4 memory
    - Support for 0x86 serdes protocol which can support following interfaces
        - 2 RGMII's on DTSEC4, DTSEC5
        - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
    - Support of DIU

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-28 14:40:57 -07:00
Fabio Estevam
42acd1874f mx6sxsabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.

Fix the variable type.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-26 12:12:04 +02:00
Fabio Estevam
e4b984d75e mx6sabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.

Fix the variable type.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-26 12:12:04 +02:00
Haikun.Wang@freescale.com
5989df7e2c armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLD
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Haikun Wang
e71a980a4d armv8/ls2085aqds: DSPI pin muxing configure through QIXIS
DSPI has pin muxing with SDHC and other IPs, this patch check the
value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check
the "hwconfig" variable. If those pins are configured to DSPI and
"hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure
the routing to on-board SPI memory. Otherwise will configure to SDHC.
DSPI is enabled in "hwconfig" by appending "dspi", eg.
setenv hwconfig "$hwconfig;dspi"

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:39 -07:00
Alison Wang
88c857df8c arm/ls102xa: Add little-endian mode support for audio IPs
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:38 -07:00
Prabhakar Kushwaha
9527931507 board/ls2085rdb: Export functions for standalone AQ FW load apps
Export functions required by Aquntia PHY firmware load application.
functions are memset, strcpy, mdelay, mdio_get_current_dev,
phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:37 -07:00
Prabhakar Kushwaha
5c05508971 armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr
The agreed split of the top of memory is 256M for debug server and 256M
 for MC. This patch implements the split.

 In addition, the MC mem must be 512MB aligned, so the amount of memory
 to hide must be 512MB to achieve that alignment.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:36 -07:00
Bhupesh Sharma
a2dc818f21 armv8/ls2085a: Expose all DDR region(s) to Linux
This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).

This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
York Sun
fc7b3855e1 armv8/ls2085ardb: Fix SPD address error on early boards
Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20 11:44:35 -07:00
Prabhakar Kushwaha
ff1b8e3f55 armv8/ls2085a: Avoid hard-coding for board name print
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.

Instead of hard-coding, board name should change as per selected
personality.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:35 -07:00
Prabhakar Kushwaha
27df54b163 armv8/ls2085RDB: Update board version print logic
As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.

So update board version print logic to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Jaiprakash Singh
b8baf460ee board/fsl/common: Fix eeprom system version endianness
SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.

So use cpu-specific APIs to read SYSTEM version.

Signed-off-by: Jaiprakash Singh <b44839 at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Prabhakar Kushwaha
d7b76e89ed armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI
FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.

Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:34 -07:00
Prabhakar Kushwaha
94540c5604 armv8/ls2085aqds: Add support of SerDes protocol 0x49
SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.

Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Yangbo Lu
5a4d744c90 armv8/ls2085ardb: add hwconfig setting for eSDHC
Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Prabhakar Kushwaha
3484d95307 armv8/ls2085ardb: Add eth & phy firmware loading support
Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20 11:44:33 -07:00
Tom Rini
9bea236b34 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-05-26 10:38:01 -04:00
York Sun
a88cc3bd90 arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
2015-05-20 10:34:09 -07:00
Peng Fan
3fd10f3e25 pmic: pfuze100 fix typo
Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-05-19 15:13:38 +02:00