Commit graph

511 commits

Author SHA1 Message Date
Stefan Roese
8ad01ce36f x86: Remove x86 specific GD flags as they are not referenced at all
This patch removes the x86 architecture specific GD flags
(GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only
GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S.
But the coreboot target does not use start16.S at all and boots directly
from the 32-bit start code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-18 21:54:10 +08:00
Park, Aiden
14360bf059 x86: slimbootloader: Set TSC information for tsc_timer
Slim Bootloader already calibrated TSC and provides it to U-Boot.
Therefore, U-Boot does not have to re-calibrate TSC.
Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass
TSC calibration and use the provided TSC frequency.
- Get TSC frequency from performance info hob
- Set tsc_base and clock_rate for tsc_timer driver

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
2869c3b3de x86: slimbootloader: Add serial driver
Slim Bootloader provides serial port info thru its HOB list pointer.
All these HOBs are eligible for Slim Bootloader based board only.
- Get serial port information from the serial port info HOB
- Leverage ns16550 driver with slimbootloader specific platform data

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
1fb17ea548 x86: slimbootloader: Add memory configuration
Slim Bootloader provides memory map info thru its HOB list pointer.
Configure memory size and relocation memory from the HOB data, and
provide e820 entries as well.
- Get memory size from the memory map info HOB
- Set available top memory lower than 4GB for U-Boot relocation
- Provide e820 entries from the memory map info HOB

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
7165fd584f x86: Add a common HOB library
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
Add a common HOB library in lib/hob.c and include/asm/hob.h.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
5b931a5080 x86: lib: fsp: Use EFI_GUID and efi_guid_t
Use existing EFI_GUID and efi_guid_t instead of struct efi_guid.
This is pre-work before making a common HOB library.
- Change 'struct efi_guid' to efi_guit_t
- Remove 'struct efi_guid'
- Define GUIDs with EFI_GUID() macro
- Use guidcmp() instead of compare_guid()
- Remove compare_guid()

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested on MinnowMax
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
544293f878 x86: Add new slimbootloader CPU type
This slimbootloader CPU type is to enable U-Boot as a payload which
runs on top of Slim Bootloader (https://github.com/slimbootloader).
The Slim Bootloader is designed with multi-stage architecture for
the execution from reset vector to OS booting, and supports QEMU,
Apollolake, Whiskeylake and Coffeelake platforms consuming Intel
FSP (https://github.com/IntelFsp) for silicon initialization
including CAR and memory initialization.
The Slim Bootloader generates new HOB (Hand Off Block) which are
serial port info, memory map info, performance data info and so on,
and passes it to a Payload. U-Boot as a payload will use these HOB
information for basic initialization such as serial console.

As an initial commit,
- Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type
- Add new arch/x86/cpu/slimbootloader directory with minimum codes
- Get hob_list pointer from Slim Bootloader

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
e3be52ceac x86: acpi: Enable ACPI companion for Intel iDMA 32-bit
ACPI has a capability to specify DMA parameters for DMA channel consumers.
To enable this for Intel Edison, describe GP DMA device in ACPI table
in order to get an ACPI handle to it in OS.

This works in conjunction with CSRT, which must be in align with DSDT.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
ddd2a4244c x86: acpi: Introduce a stub to generate CSRT
Here is a stub function that generates an empty CSRT. If the target platform
provides acpi_fill_csrt() function, it will be used to populate the table.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
eef3007945 x86: acpi: Add CSRT description
Add CSRT [1] description as it provided in Linux kernel.

[1]: http://www.uefi.org/sites/default/files/resources/CSRT%20v2.pdf

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Simon Glass
44c6a0ed6e x86: Add a forward struct declaration in coreboot_tables.h
This struct is not defined in this header file. Add a forward declaration
so that it can be included in any context.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-10 16:52:58 -06:00
Simon Glass
7c03caf6fa x86: Add a simple TPL implementation
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:18 +08:00
Simon Glass
9a67994e01 x86: Support saving MRC data from SPL
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:14 +08:00
Simon Glass
62be5dd885 x86: Add a handoff header file
Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:12 +08:00
Simon Glass
c0069e9a8a x86: Add a way to reinit the cpu
We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:11 +08:00
Andy Shevchenko
c652dd1557 x86: acpi: Add DMA descriptors for I2C1 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Note, I2C6, which is available to user, has no DMA request lines connected.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
1d2825aa30 x86: acpi: Add DMA descriptors for SPI5 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Simon Glass
3f3411ebf8 x86: broadwell: Add support for serial I/O devices
Add support for initing the I2C device and ADSP on broadwell. These are
needed for sound to work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
23e8bd7e49 x86: broadwell: Add support for the ADSP
The Application Digital Signal Processor is used for sound processing with
broadwell. Add a driver to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
79a5be820d sound: x86: Add beeping support in i8254
Adjust the code to allow beeping at different frequencies, using a
calculated value for timer 2.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
6744c0d652 sound: x86: link: Add sound support
Add sound support for link, using the HDA codec implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
3a44bfdf08 x86: Adjust I/O macros to work on 64-bit machines
At present these macros give warnings on 64-bit machines and do not
correctly do 32-bit accesses. Update them to use linux types.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:29 +08:00
Heinrich Schuchardt
6b59607f10 x86: do not use i386 code for x86_64 memory functions
arch/x86/lib/string.c contains assembler implementations of memcpy(),
memmove(), and memset() written for i386. Don't use it on x86_64.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13 09:40:06 +01:00
Andy Shevchenko
24b56e2bf3 x86: tangier: Add initial ACPI support for PMIC device
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS
and access is going via SCU device, enumerated via PCI.

For now, we add just a minimum support of PMIC device to allow enabling,
e.g. USB OTG, in the OS.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12 14:37:17 +08:00
Andy Shevchenko
73af0601e1 x86: acpi: Fix indentation in Intel Tangier ASL code
Make the indentation aligned with what used elsewhere in U-Boot.

No functional change intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10 10:12:29 +08:00
Andy Shevchenko
f1b8641fd4 x86: acpi: Enable RTC for Intel Tangier
Intel Tangier SoC has RTC inside. So, enable it in ACPI.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-10 10:12:29 +08:00
Andy Shevchenko
b288cd9600 x86: acpi: Generate SPCR table
Microsoft specifies a SPCR (Serial Port Console Redirection Table) [1].
Let's provide it in U-Boot.

[1]: https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-12-05 07:23:16 -07:00
Andy Shevchenko
f3275aa4a1 x86: acpi: Add SPCR table description
Add SPCR table description as it provided in Linux kernel.

Port subtype for ACPI_DBG2_SERIAL_PORT is used as an interface type in SPCR.
Thus, provide a set of definitions to be utilized later.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-05 07:23:16 -07:00
Bin Meng
3bf9a8e846 x86: Implement arch-specific io accessor routines
At present the generic io{read,write}{8,16,32} routines only support
MMIO access. With architecture like x86 that has a separate IO space,
these routines cannot be used to access I/O ports.

Implement x86-specific version to support both PIO and MMIO access,
so that drivers for multiple architectures can use these accessors
without the need to know whether it's MMIO or PIO.

These are ported from Linux kernel lib/iomap.c, with slight changes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-14 09:16:27 -08:00
Andy Shevchenko
24109bba6a x86: acpi: Remove redundant Offset (0x00)
New ACPI assembler issues a warning:

board/intel/edison/dsdt.asl.tmp     13:     Offset (0x00),
Remark   2158 -                                       ^ Unnecessary/redundant use of Offset operator

Indeed, in the OperationRegion the offset is 0x00 by default.

Thus, drop unneeded Offset() use as suggested by ACPI assembler.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-06 13:35:06 +08:00
Stefan Roese
7d2a0534a6 x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region
To allow bigger 64 bit prefetchable PCI regions in Linux, this patch
changes the base address and range of the ACPI area passed to Linux.
BayTrail can only physically access 36 bit of PCI address space. So
just chaning the range without changing the base address won't work
here, as 0xf.ffff.ffff is already the maximum address.

With this patch, a maximum of 16 GiB of local DDR is supported. This
should be enough for all BayTrail boards though.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-28 21:02:15 +08:00
Simon Glass
590cee8315 x86: Update mtrr functions to allow leaving cache alone
At present the mtrr functions disable the cache before making changes and
enable it again afterwards. This is fine in U-Boot, but does not work if
running in CAR (such as we are in SPL).

Update the functions so that the caller can request that caches be left
alone.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-09 04:40:27 -06:00
Georgii Staroselskii
f7ce2d6e65 x86: tangier: acpi: add I2C6 node
Now that we have I2C#6 working, it's time to add a corresponsing
ACPI binding.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 17:35:53 +08:00
Georgii Staroselskii
224742a390 x86: cpu: introduce scu_ipc_raw_command()
This interface will be used to configure properly some pins on
Merrifield that are shared with SCU.

scu_ipc_raw_command() writes SPTR and DPTR registers before sending
a command to SCU.

This code has been ported from Linux work done by Andy Shevchenko.

Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-17 14:34:15 +08:00
Masahiro Yamada
3747bdbb2b arch: types.h: factor out fixed width typedefs to int-ll64.h
All architectures have the same definition for s8/16/32/64
and u8/16/32/64.

Factor out the duplicated code into <asm-generic/int-ll64.h>.

BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:16 -04:00
Masahiro Yamada
9865543ae6 Remove CONFIG_USE_STDINT
You do not need to use the typedefs provided by compiler.

Our compilers are either IPL32 or LP64.  Hence, U-Boot can/should
always use int-ll64.h typedefs like Linux kernel, whatever the
typedefs the compiler internally uses.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:16 -04:00
Bin Meng
e69cc6bc42 x86: zimage: Remove acpi_rsdp_addr propagation to kernel boot parameters
As of today, the proposal of adding "acpi_rsdp_addr" to the kernel
boot protocol does not make its way to the kernel mainline. This
creates some confusion if we leave it in the U-Boot code base.
Remove it for now until we have a clear picture with kernel upstream.

Note this eventually does a partial revert to commit 3469bf4274
("x86: zImage: Propagate acpi_rsdp_addr to kernel via boot parameters")

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-30 11:23:15 +08:00
Bin Meng
1fdeacd32c x86: zimage: Support booting Linux kernel from an EFI payload
At present Linux kernel loaded from U-Boot as an EFI payload does
not boot. This fills in kernel's boot params structure with the
required critical EFI information like system table address and
memory map stuff so that kernel can obtain essential data like
runtime services and ACPI table to boot.

With this patch, now U-Boot as an EFI payload becomes much more
practical: it is another option of kernel bootloader, ie, can be
a replacement for grub.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-08-30 11:23:14 +08:00
Alexander Graf
dae73c4cdc elf: Move x86 reloc defines to common elf.h
We need to know about x86 relocation definitions even in cases where
we don't officially build against the x86 target, such as with sandbox.

So let's move the x86 definitions into the common elf header, where all
other architectures already have them.

Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Bin Meng
05855fd31a x86: acpi: Prevent acpi_table.h from being included more than once
The wrapper #ifndef is currently missing in acpi_table.h. Add it to
prevent it from being included multiple times.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-20 09:33:22 +08:00
Bin Meng
a0609a8d19 x86: acpi: Move APIs unrelated to ACPI tables generation to a separate library
acpi_find_fadt(), acpi_find_wakeup_vector() and enter_acpi_mode()
are something unrelated to ACPI tables generation. Move these to
a separate library.

This also fixes several style issues reported by checkpatch in the
original codes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Bin Meng
b37b7b2063 x86: Switch to use DM sysreset driver
This converts all x86 boards over to DM sysreset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-20 09:33:22 +08:00
Ivan Gorinov
8199a145c4 x86: Use microcode update from device tree for all processors
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.

If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-07-02 09:23:28 +08:00
Bin Meng
5460fd0762 x86: Change __kernel_size_t conditionals to use compiler provided defines
Since commit bb0bb91cf0 ("efi_stub: Use efi_uintn_t"), EFI x86
64-bit payload does not work anymore. The call to GetMemoryMap()
in efi_stub.c fails with return code EFI_INVALID_PARAMETER. Since
the payload itself is still 32-bit U-Boot, efi_uintn_t gets wrongly
interpreted as int, but it should actually be long in a 64-bit EFI
environment.

This changes the x86 __kernel_size_t conditionals to use compiler
provided defines instead. That way we always adhere to the build
environment we're in and the definitions adjust automatically.

Fixes: bb0bb91cf0 ("efi_stub: Use efi_uintn_t")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-24 08:56:04 +08:00
Ivan Gorinov
964927323f x86: Add 64-bit setjmp/longjmp implementation
Add setjmp/longjmp functions for x86_64.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-24 08:56:04 +08:00
Bin Meng
51050ff0a2 x86: irq: Support discrete PIRQ routing registers via device tree
Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume
consecutive PIRQ routing control registers. But this is not always
the case on some platforms. Introduce a new device tree property
intel,pirq-regmap to describe how the PIRQ routing register offset
is mapped to the link number and adjust the irq router driver to
utilize the mapping.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Bin Meng
dcec5d565a x86: irq: Parse number of PIRQ links from device tree
The "intel,pirq-link" property in Intel IRQ router's dt bindings
has two cells, where the second one represents the number of PIRQ
links on the platform. However current driver does not parse this
information from device tree. This adds the codes to do the parse
and save it for future use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Bin Meng
594d089c8a x86: irq: Change LINK_V2N and LINK_N2V to inline functions
LINK_V2N and LINK_N2V are currently defines, so they cannot handle
complex logics. Change to inline functions for future extension.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Bin Meng
bc728b1bc0 x86: irq: Remove chipset specific irq router drivers
At present there are 3 irq router drivers. One is the common one
and the other two are chipset specific for queensbay and quark.
However these are really the same drivers as the core logic is
the same. The two chipset specific drivers configure some registers
that are outside the irq router block which should really be part
of the chipset initialization.

Now we remove these specific drivers and make all x86 boards use
the common one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Simon Glass
329da4850c Define board_quiesce_devices() in a shared location
This undocumented function relies on arch-specific code to declare a nop
weak version. Add the weak function in common code instead to avoid having
to duplicate the same function in each arch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-06-03 15:27:21 +02:00