When building U-Boot host tools for Windows from Microsoft Azure
Pipelines, we see tons of weird warnings and errors emitted from
every Kconfig files:
Kconfig:6:warning: ignoring unsupported character ''
Kconfig:6:warning: ignoring unsupported character ''
Kconfig:8:warning: ignoring unsupported character ''
Kconfig:9:warning: ignoring unsupported character ''
Kconfig:10:warning: ignoring unsupported character ''
Kconfig:10:warning: ignoring unsupported character ''
Kconfig:13:warning: ignoring unsupported character ''
arch/Kconfig:1:warning: ignoring unsupported character ''
arch/Kconfig:2:warning: ignoring unsupported character ''
arch/Kconfig:2:warning: ignoring unsupported character ''
arch/Kconfig:4:warning: ignoring unsupported character ''
...
After several rounds of experiments, it turns out this is caused
by line endings. Historically, Linux and macOS used linefeed (LF)
characters while Windows used a carriage return plus a linefeed
(CRLF). When Azure Pipelines checks out the U-Boot repo, Git tries
to compensate for the difference by automatically making lines end
in CRLF in the working directory on Windows, which confuses the
Kconfig file parsing logic.
Fortunately Git provides a way for repos to tell Git not to do such
automatical line endings conversion via .gitattributes file below:
* text eol=lf
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This adds a reST document for how to build U-Boot host tools,
including information for both Linux and Windows.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
'struct ustat' uses linux-specific typedefs to declare its memebers:
__kernel_daddr_t and __kernel_ino_t. It is currently not used by any
U-Boot codes, but when we build U-Boot tools for other platform like
Windows, this becomes a problem.
Let's surround it with __linux__.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
__swab32() is a Linux specific macro defined in linux/swab.h. Let's
use the compiler equivalent builtin function __builtin_bswap32() for
better portability.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
__leXX has Linux kernel specific __attribute__((bitwise)) which is
not portable. Use corresponding uintXX_t instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Use log() insted of debug() for uclass_find_device_by_seq function,
since this print is very much and we can filter it out with log()
interface.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move #define to top of file as per docs:
Signed-off-by: Simon Glass <sjg@chromium.org>
There is a contributor in Linux kernel with a comma in their name, which
confuses patman and results in invalid to- or cc- addresses on some
patches. To avoid this, let's use \0 as a separator when generating cc
file.
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
It is possible to enable bootstage in TPL. TPL can stash the info for SPL.
But at present this information is then lost because SPL does not read
from the stash.
Add support for SPL not being the first phase to enable bootstage.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootstage in TPL and SPL use the same ID so it is not possible
to see the timing of each. Separate out the IDs and use the correct one
depending on which phase we are at.
Example output:
Timer summary in microseconds (14 records):
Mark Elapsed Stage
0 0 reset
224,787 224,787 TPL
282,248 57,461 end TPL
341,067 58,819 SPL
925,436 584,369 end SPL
931,710 6,274 board_init_f
1,035,482 103,772 board_init_r
1,387,852 352,370 main_loop
1,387,911 59 id=175
Accumulated time:
196 dm_r
8,300 dm_spl
14,139 dm_f
229,121 fsp-m
262,992 fsp-s
Signed-off-by: Simon Glass <sjg@chromium.org>
At present bootstage relocation assumes that it is possible to point back
to memory available before relocation, so it does not relocate the
strings. However this is not the case on some platforms, such as x86 which
uses the cache as RAM and loses access to this when the cache is enabled.
Move the relocation step to before U-Boot relocates, expand the allocated
region to include space for the strings and relocate the strings at the
same time as the bootstage records.
This ensures that bootstage data can remain accessible from TPL through
SPL to U-Boot before/after relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present there is a single shared address for bootstage data in both
TPL and SPL. If SPL unstashs TPL bootstage info and then stashes it again
to pass it to U-Boot, the new stash overwrites the strings of the old
stash.
Fix this by duplicating the strings into the malloc() region. This should
be a small code. Fix the header-file order at the same time.
This problem doesn't happen at the next stage (SPL->U-Boot) since U-Boot
relocates the boostage data.
Signed-off-by: Simon Glass <sjg@chromium.org>
The current code searches for empty records but these not existing with
bootstage now. This used to be needed when bootstage records were stored
in a spare array.
Drop the unnecessary code and fix a code-style nit at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
When stashing bootstage info, store the next ID so that it can be used
when the stash is restored. This avoids the ID starting at zero and
potentially overwriting existing entries.
Signed-off-by: Simon Glass <sjg@chromium.org>
Make sure that the bloblist starts on an aligned boundary. This protects
against one of the early allocating causing the alignment to be lost.
Signed-off-by: Simon Glass <sjg@chromium.org>
With a bit of code reordering we can support %p using the existing code
for ulong.
Move the %p code up and adjust the logic accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is used in the bootstage report which may be trigged in TPL
or TPL. Add a very basic implication of this function so that it builds.
There is no attempt to get the formatting right, since this would add too
much code size.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
The ctype array is brought into the image, adding 256 bytes, when it is
unlikely to be needed. The extra code for %p is only present when DEBUG
is defined, so let's drop ctype as well unless DEBUG is defined.
Signed-off-by: Simon Glass <sjg@chromium.org>
The test did reads after writes but didn't check the value.
It probably was because the sandbox didn't implement the writeX/readX
functions.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Updated to use sandbox_set_enable_memio():
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This function assumes that the 'val' parameter has no masked bits set.
This is not defined by the function prototype though. Fix the function to
mask the value and update the documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
This function needs a prototype so that tests can use it. Add one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function writes to its address so the address should not be declared
as const. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Quite a few tests use addresses or hex values for comparisons. Add hex
output for test failures, e.g.:
0x55ca22fa == reg: Expected 0x55ca22fa (1439310586),
got 0x55ea22fb (1441407739)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiQkHUH+J02LLC9InKPlOlyTyXBgFAl2zFisACgkQKPlOlyTy
XBgf9RAAkNwLjqUcBz3Ob1briRG5HF4D6bZCpjtkTIO8a2fanUHbSehh30TX8x2X
z0t/9Sd4OZwAeTxfQ/AlbbVdiB9IMgEb6lJ30Vr88MRNoPhABIQ8hw5xAzFi/6x9
88YolS/HQo6iR9rzSlaKjdIHhPTH5oQzRJ3JLqSwZzfUNy+zqINEhs3SYCnD2lyV
gTgiIT3Y5nKrhVHPUCy+jQG+wwWej2NFgwn71vR3/PSQJwxBuasg0qqOKD9hRtpC
XL6VErE7bf00elO8xjEObYrmB2FpffXJdkazS2HtRYNyKx0quaRNXJt7wqxEVP9L
M6SmL+S7zBFAetc/iyrlaakPvn7ImehSZkgLYaTPc3yzO+6bgq9tLfBERn/B/s5g
YyIzPGF66L96nuu0eVGCgSoUBjzBE8l2QTI8dho5xJxjWAUJOWSB0egqfFZzYVFu
4X37w6Z0j6uTK2oEl7KgJdc0JsZRsAJ8ZiqgOeNeMUTl2RnjGt0Oa7E24Va3n3hM
5vuEba9nPUFmdC5vlSd2RUK/dB587uKV93r5j54U62clpbiK+VMaRuRVX64ytZvB
B/0fKyCu+y7bxeZe4/X27jBUOk5yCuxbNI66m+cnnvfHqEmhz5PfDCEK1Dr29oqf
sCJLgTr7ahyuW4kEoL7KCOBEugPI85fp8/OlqC63M6/Kft0w5sA=
=6G/J
-----END PGP SIGNATURE-----
Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
Add the address spaces for the R5F cores in MCU domain to the ranges
property of the cbass_mcu interconnect node so that the addresses
within the R5F nodes can be translated properly by the relevant OF
address API.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.
Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.
Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Added training support for LPDDR4 and DDR3L DDRs. Also added/changed
some register configuration to support all 3 DDR types
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.
Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.
The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.
Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Once the arch specific boot_prepare_linux completes, boards wants to
have a custom preparation for linux. Add support for a custom
board_prep_linux.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Expand SPL_MULTI_DTB_FIT to accommodate usb peripheral nodes being
added to support SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add usb peripheral and usb phy nodes in spl to enable SPL_DFU bootmode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJdspnqAAoJEB6zHgIOrC/Ixi4IAJEEiCZPu6Z3fbkFX/Um7vCX
eMTltJN8nz4oiSi3xdx3ejueqWdW3F8VuCkHb0j0bVAhMlUlVgwCzfd0cD+D2iwS
jkrgzASNAr+JeYKYEdWqqfaUxOCd2qfuBu9EXlpvKQLWLt+KRfsOsHWcgR4bf095
aGCihvd/fKhKYUvbf5cEQnsWa3UwtsKk4Web5MKjxXx3p0iVNlu4KLd/vDWfTios
X1NqiO5ZjXNrDxyG6Aj8lgDXlE5kfeKaN/aCJU1/0U2cXm8JRu2w2dv1P/e/kU+j
NHIGzICAG4Lk/4gQTeuohJxLyvj7K3i1H12ik9Qeh4H1/5fsyybyltGUo7H443s=
=JYe3
-----END PGP SIGNATURE-----
Merge tag 'u-boot-atmel-2020.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features and fixes for 2020.01 cycle
This feature set includes Eugen's work on a new tiny flexcom driver and
eeprom mac retrieval for the sam9x60-ek board.
Some configs are selected in Kconfig and is no longer needed in the
defconfig files. Some configs (power domain, ram) are never used.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the
system, they should be always selected.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This patch adds default eth pinctrl for all boards.
There are two pinctrl nodes used for two scenarios:
ephy_iot_mode - for IOT boards which have only one port (PHY0)
ephy_router_mode - For routers which have more than one ports
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
