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16140 commits

Author SHA1 Message Date
Nishanth Menon
3acb553439 OMAP4460: TPS Ensure SET1 is selected after voltage configuration
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
                           |---------------| (SET1 default 1.4V)
                           |               --------(programmed voltage)
                           | <- (This switch happens on mux7,pullup)
vdd_mpu(TPS)         -----/ (OPP boot voltage)
                                             --------- (programmed voltage)
vdd_core(TWL6030)    -----------------------/ (OPP boot voltage)
Problem 1)                |<----- Tx ------>|
   timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.

By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
                                  -------- (programmed voltage)
vdd_mpu(TPS)         ------------/ (Opp boot voltage)
                                   --------- (programmed voltage)
vdd_core(TWL6030)    -------------/ (OPP boot voltage)

NOTE: This does not attempt to address OMAP5 - Aneesh please confirm

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Nishanth Menon
a78274b205 OMAP3+: Introduce generic logic for OMAP voltage controller
OMAP Voltage controller is used to generically talk to
PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code
in multiple SoC code, introduce a common voltage controller
logic which can be re-used from elsewhere.

With this change, we replace setup_sri2c with omap_vc_init which
has the same functionality, and replace the voltage scale
replication in do_scale_vcore and do_scale_tps62361 with
omap_vc_bypass_send_value. omap_vc_bypass_send_value can also
now be used with any configuration of PMIC.

NOTE: Voltage controller controlling I2C_SR is a write-only data
path, so no register read operation can be implemented.

Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2012-05-15 08:31:22 +02:00
Jonathan Solnit
bbbc1ae921 ARM:OMAP+:MMC: Add parameters to MMC init
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency.  While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board.  The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.

Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
2012-05-15 08:31:22 +02:00
David Purdy
1d0f5fa11d kirkwood: add support for Cloud Engines Pogoplug E02
This patch adds support for Cloud Engines Pogoplug E02

Information regarding the CE Pogoplug E02 board can be found at:
http://archlinuxarm.org/platforms/armv5/pogoplug-v2-pinkgray

Signed-off-by: Dave Purdy <david.c.purdy@gmail.com>
Cc: prafulla@marvell.com
Cc: albert.u.boot@aribaud.net
2012-05-15 08:31:22 +02:00
Luka Perkov
e5841e1211 kirkwood: add NAS62x0 board support
Add support for new boards RaidSonic ICY BOX NAS6210 and NAS6220.

NAS6210 has 1 SATA and 1 eSATA port while NAS6220 has 2 SATA ports.

More information about the boards can be found here:

http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7036
http://www.raidsonic.de/en/products/nas-systems.php?we_objectID=7515

Signed-off-by: Luka Perkov <uboot@lukaperkov.net>
Signed-off-by: Gerald Kerma <dreagle@doukki.net>
Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
2012-05-15 08:31:22 +02:00
Vladimir Zapolskiy
463ec1caa3 devkit3250: add Timll DevKit3250 board initial support
This change adds a basic support for Embest/Timll DevKit3250 board,
NOR and UART are the only supported peripherals for a moment. The board
doesn't require low-level init, because the initial SDRAM and GPIO
configuration is performed during kickstart bootloader execution.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-05-15 08:31:22 +02:00
Vladimir Zapolskiy
cc35fdbc4d serial: add LPC32X0 high-speed UART devices support
This change adds an implementation of high-speed UART found on NXP
LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-05-15 08:31:21 +02:00
Vladimir Zapolskiy
52f69f818c arm926ejs: add NXP LPC32x0 cpu series support
This change adds initial support for NXP LPC32x0 SoC series.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2012-05-15 08:31:21 +02:00
Ian Campbell
5f2e142527 ARM: dreamplug: Enable FDT support
I have tested booting both FDT and non-FDT based Linux kernels (based on
http://marc.info/?l=linux-arm-kernel&m=133002679716986 and
http://marc.info/?l=linux-arm-kernel&m=132328894303581 respectively).

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Jason <jason@lakedaemon.net>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
2012-05-15 08:31:21 +02:00
Wolfgang Denk
0a6deb3251 Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
  lin_gadget: use common linux/compat.h
  linux/compat.h: rename from linux/mtd/compat.h
  lin_gadget: use common mdelay
  gunzip: rename z{alloc, free} to gz{alloc, free}
  fs/fat: align disk buffers on cache line to enable DMA and cache
  part_dos: align disk buffers on cache line to enable DMA and cache
2012-04-30 18:19:28 +02:00
Wolfgang Denk
e0f6a4e8b1 Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
  powerpc/ppc4xx: Remove typedefs for gdsys FPGA
  powerpc/ppc4xx: Fix typo in gdsys_fpga.h
  powerpc/ppc4xx: Update gdsys board configurations
  powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
  powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
  powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
  powerpc/ppc4xx: Adjust environment size on neo
2012-04-30 16:55:37 +02:00
Wolfgang Denk
4212657c53 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
* 'master' of git://git.denx.de/u-boot-ppc4xx:
  powerpc/ppc4xx: Remove typedefs for gdsys FPGA
  powerpc/ppc4xx: Fix typo in gdsys_fpga.h
  powerpc/ppc4xx: Update gdsys board configurations
  powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
  powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
  powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
  powerpc/ppc4xx: Adjust environment size on neo
2012-04-30 16:55:25 +02:00
Mike Frysinger
6777a3cf73 lin_gadget: use common linux/compat.h
Merge our duplicate definitions with the common header.

Also fix drivers/usb/gadget/s3c_udc_otg_xfer_dma.c to
use min() instead of min_t() since we remove the latter
from compat.h.

Additionally use memalign() directly as the lin_gadget
specific kmalloc() macro is removed from lin_gadget_compat.h
by this patch.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
2012-04-30 16:54:51 +02:00
Mike Frysinger
7b15e2bb9b linux/compat.h: rename from linux/mtd/compat.h
This lets us use it in more places than just mtd code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-30 16:54:51 +02:00
Mike Frysinger
4e2c05873a lin_gadget: use common mdelay
No need to provide our own mdelay() macro when we have a func for it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-30 16:54:51 +02:00
Mike Frysinger
e3ed0575a7 gunzip: rename z{alloc, free} to gz{alloc, free}
This allows us to add a proper zalloc() func (one that does a zeroing
alloc), and removes duplicate prototypes.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-30 16:54:51 +02:00
Eric Nelson
9a800ac718 fs/fat: align disk buffers on cache line to enable DMA and cache
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-04-30 16:54:50 +02:00
Eric Nelson
dec049d924 part_dos: align disk buffers on cache line to enable DMA and cache
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-04-30 16:54:50 +02:00
Andy Fleming
f588bb034d Allow for parallel builds and saved output
The MAKEALL script cleverly runs make with the appropriate options
to use all of the cores on the system, but your average U-Boot build
can't make much use of more than a few cores.  If you happen to have
a many-core server, your builds will leave most of the system idle.

In order to make full use of such a system, we need to build multiple
targets in parallel, and this requires directing make output into
multiple directories. We add a BUILD_NBUILDS variable, which allows
users to specify how many builds to run in parallel.
When BUILD_NBUILDS is set greater than 1, we redefine BUILD_DIR for
each build to be ${BUILD_DIR}/${target}. Also, we make "./build" the
default BUILD_DIR when BUILD_NBUILDS is greater than 1.

MAKEALL now tracks which builds are still running, and when one
finishes, it starts a new build.

Once each build finishes, we run "make tidy" on its directory, to reduce
the footprint.

As a result, we are left with a build directory with all of the built
targets still there for use, which means anyone who wanted to use
MAKEALL as part of a test harness can now do so.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-30 16:52:19 +02:00
Wolfgang Denk
05f132d74d Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
  powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
  powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
  cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
  PowerPC: correct the SATA for p1/p2 rdb-pc platform
  powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
  powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
  powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
  powerpc/corenet_ds: Slave module for boot from SRIO
  powerpc/corenet_ds: Master module for boot from SRIO
  powerpc/corenet_ds: Document for the boot from SRIO
  powerpc/corenet_ds: Correct the compilation errors about ENV
  powerpc/srio: Rewrite the struct ccsr_rio
  powerpc/85xx:Fix lds for nand boot debug info
  powerpc/p2041rdb: add env in NAND support
  powerpc/p2041rdb: add NAND and NAND boot support
  powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
  powerpc/85xx:Avoid vector table compilation for nand_spl
  powerpc/85xx:Fix IVORs addr after vector table relocation
  powerpc/85xx:Avoid hardcoded vector address for IVORs
  powerpc/p1023rds: Disable nor flash node and enable nand flash node
2012-04-30 16:45:59 +02:00
Wolfgang Denk
5f6db68b42 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
  powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
  cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
  PowerPC: correct the SATA for p1/p2 rdb-pc platform
  powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
  powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
  powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
  powerpc/corenet_ds: Slave module for boot from SRIO
  powerpc/corenet_ds: Master module for boot from SRIO
  powerpc/corenet_ds: Document for the boot from SRIO
  powerpc/corenet_ds: Correct the compilation errors about ENV
  powerpc/srio: Rewrite the struct ccsr_rio
  powerpc/85xx:Fix lds for nand boot debug info
  powerpc/p2041rdb: add env in NAND support
  powerpc/p2041rdb: add NAND and NAND boot support
  powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
  powerpc/85xx:Avoid vector table compilation for nand_spl
  powerpc/85xx:Fix IVORs addr after vector table relocation
  powerpc/85xx:Avoid hardcoded vector address for IVORs
  powerpc/p1023rds: Disable nor flash node and enable nand flash node
2012-04-30 16:45:56 +02:00
Wolfgang Denk
3f8550c5e9 Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
  i2c:designware Turn off the ctrl when setting the speed
  i2c: Add support for designware i2c controller
  sh: i2c: Add support I2C controller of SH7734
2012-04-30 16:43:52 +02:00
Wolfgang Denk
04a9cb8c59 Merge branch 'master' of git://git.denx.de/u-boot-i2c
* 'master' of git://git.denx.de/u-boot-i2c:
  i2c:designware Turn off the ctrl when setting the speed
  i2c: Add support for designware i2c controller
  sh: i2c: Add support I2C controller of SH7734
2012-04-30 16:43:49 +02:00
Wolfgang Denk
0cdf37ba09 Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians:
  Blackfin: bfin_sdh: drop dos part hardcode
  Blackfin: move gd/bd to bss by default
  Blackfin: gd_t: relocate volatile markings
2012-04-30 16:41:25 +02:00
Wolfgang Denk
99310d1448 Merge branch 'master' of git://git.denx.de/u-boot-blackfin
* 'master' of git://git.denx.de/u-boot-blackfin:
  Blackfin: bfin_sdh: drop dos part hardcode
  Blackfin: move gd/bd to bss by default
  Blackfin: gd_t: relocate volatile markings
2012-04-30 16:41:23 +02:00
Mike Frysinger
314f634b48 image/fit: drop inline markings on parser code
Putting "inline" on extern funcs makes no sense, so drop them.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-04-30 16:38:54 +02:00
Wolfgang Denk
4868049309 Merge branch 'master' of git://git.denx.de/u-boot-nds32
* 'master' of git://git.denx.de/u-boot-nds32:
  board/adp-ag102: add configuration of adp-ag102
  board/adp-ag102: add board specific files
  nds32/ag102: add ag102 soc support
  nds32/ag102: add header support of ag102 soc
2012-04-30 16:29:16 +02:00
Dirk Eibach
0e60aa85c8 powerpc/ppc4xx: Remove typedefs for gdsys FPGA
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:01:29 +02:00
Dirk Eibach
530846b3c7 powerpc/ppc4xx: Fix typo in gdsys_fpga.h
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:01:23 +02:00
Dirk Eibach
996d88d810 powerpc/ppc4xx: Update gdsys board configurations
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:01:17 +02:00
Dirk Eibach
2ade7bee15 powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
In hardware revision 1.20 one more fan controller is added to dlvision-10g.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:01:11 +02:00
Dirk Eibach
b19bf8344f powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
Print fpga info at last_stage_init on gdsys 405ep boards.
Use dtt_init() to startup fans.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:01:03 +02:00
Dirk Eibach
6e9e6c36a6 powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
In order to add boards that have different hardware for fpga reset,
any 405ep gdsys board now provides these functions:

void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:00:56 +02:00
Dirk Eibach
00251261e2 powerpc/ppc4xx: Adjust environment size on neo
Environment size on neo has to be 0x20000 for compatibilty reasons.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-04-30 15:00:49 +02:00
Vikram Narayanan
330a091c11 patman: Change the location of patman path
Fix the location of patman path in README

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2012-04-30 09:57:48 +02:00
Vikram Narayanan
1713247ffe patman: Fix a typo error
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2012-04-30 09:39:31 +02:00
Marek Vasut
b68d63ce4b GCC47: Fix warning in md5.c
md5.c: In function ‘MD5Final’:
md5.c:156:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]
md5.c:157:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-04-29 14:14:08 +02:00
Marek Vasut
f624dd15e3 GCC47: Fix warning in cmd_nand.c
cmd_nand.c: In function ‘arg_off_size’:
cmd_nand.c:216:5: warning: ‘maxsize’ may be used uninitialized in this function [-Wmaybe-uninitialized]

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
2012-04-29 14:13:53 +02:00
Wolfgang Denk
e654fac2e6 Merge branch 'marex@denx.de' of git://git.denx.de/u-boot-staging
* 'marex@denx.de' of git://git.denx.de/u-boot-staging:
  CMD: CONFIG_CMD_SETECPR -> CONFIG_CMD_SETEXPR on omap3_logic
  CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE
  CMD: Fix typo CMD_FSL -> CMD_MFSL in readme
  HWW1U1A: Fix CMD_SHA1 -> CMD_SHA1SUM
  CMD: Remove CMD_LOG, it's unused
  CMD: Fix typo KGBD -> KGDB on debris board
  CMD: Drop CONFIG_CMD_EMMC, it's not used
  CMD: Drop CONFIG_CMD_DFL, it's not used
  CMD: Drop CMD_DCR, it's not used
  CMD: Drop CMD_CAN, it's not used
  CMD: Remove CMD_AUTOSCRIPT, it's not used
  AT91: Drop AT91_SPIMUX command from cmd_all
2012-04-29 14:12:10 +02:00
Wolfgang Denk
415d386877 Prepare v2012.04.01
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-04-25 15:22:50 +02:00
Timur Tabi
822ad60f1c powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but
that register does not exist on e500v1.

Signed-off-by: Timur Tabi <timur@freescale.com>
2012-04-24 23:58:34 -05:00
Timur Tabi
5d065c3e10 powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time.  The board-specific code is
deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:34 -05:00
Timur Tabi
34e210f5bd cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
Some Freescale SOCs support 32-bit and 36-bit physical addressing, and
U-Boot must be built to enable one or the other.  Add this information
to the bdinfo command.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:34 -05:00
Jerry Huang
befb7d9f3c PowerPC: correct the SATA for p1/p2 rdb-pc platform
For p1/p2 rdb-pc platform, use the PCIe-SATA Silicon Image SATA controller.
Therefore, the SATA driver will use sata_sil, instead sata_sil3114.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
2012-04-24 23:58:34 -05:00
Liu Gang
5056c8e068 powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.

Master needs to:
	1. Set outbound SRIO windows in order to configure slave's registers
	   for the core's releasing.
	2. Check the SRIO port status when release slave core, if no errors,
	   will implement the process of the slave core's releasing.
Slave needs to:
	1. Set all the cores in holdoff by RCW.
	2. Be powered on before master's boot.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
0a85a9e705 powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
When boot from SRIO, slave's ENV can be stored in master's memory space,
then slave can fetch the ENV through SRIO interface.

NOTE: Because the slave can not erase, write master's NOR flash by SRIO
	  interface, so it can not modify the ENV parameters stored in
	  master's NOR flash using "saveenv" or other commands.

Master needs to:
	1. Put the slave's ENV into it's own memory space.
	2. Set an inbound SRIO window covered slave's ENV stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode and ENV from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
3f1af81b80 powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.

Master needs to:
	1. Put the slave's ucode image into it's own memory space.
	2. Set an inbound SRIO window covered slave's ucode stored in master's
	   memory space.
Slave needs to:
	1. Set a specific TLB entry in order to fetch ucode from master.
	2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
292dc6c501 powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.
	5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
	   locally.

For the slave module, need to finish these processes:
	1. Set the boot location to SRIO1 or SRIO2 by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
	4. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_SLAVE_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:33 -05:00
Liu Gang
5ffa88eca7 powerpc/corenet_ds: Master module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2012-04-24 23:58:32 -05:00
Liu Gang
006f37f698 powerpc/corenet_ds: Document for the boot from SRIO
This document describes the implementation of the boot from SRIO,
includes the introduction of envionment, an example based on P4080DS
platform, an example of the slave's RCW, and the description about
how to use this feature.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
2012-04-24 23:58:32 -05:00